Specifications

18 EPSON S1C60N04 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
4.6 LCD Driver (COM0–COM3, SEG0–SEG25)
4.6.1 Configuration of LCD driver
The S1C60N04 has four common pins and 26 (SEG0–SEG25) segment pins, so that an LCD with a maxi-
mum of 104 (26 × 4) segments can be driven. The power for driving the LCD is generated by the CPU
internal circuit, so there is no need to supply power externally.
The driving method is 1/4 duty (or 1/3, 1/2 duty by mask option) dynamic drive, adopting the four
types of potential (1/3 bias), V
DD, VL1, VL2 and VSS. Moreover, the 1/2 bias dynamic drive that uses three
types of potential, V
DD, VL1 = VL2 and VSS, can be selected by setting the mask option (drive duty can also
be selected from 1/4, 1/3 or 1/2).
The LCD drive voltages V
L1 and VL2 are generated by the power divider inside the IC. However it is
necessary to turn the power divider on by writing 1 to the PDON register before starting LCD display.
The frame frequency is about 30.5 Hz for 1/4 duty and 1/2 duty, and 40.7 Hz for 1/3 duty (in the case of
fosc = 2 MHz), tolerance is within 5%.
Figures 4.6.1.1 to 4.6.1.6 show the drive waveform for each duty and bias.
Note: "fosc" indicates the oscillation frequency of the oscillation circuit.