MF1517-01 CMOS 32-BIT SINGLE CHIP MICROCOMPUTER S1C33210 Technical Manual S1C33210 PRODUCT PART S1C33210 FUNCTION PART
NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
S1C33210 Technical Manual This manual describes the hardware specifications of the Seiko Epson original 32-bit microcomputer S1C33210. S1C33210 PRODUCT PART Describes the hardware specifications of the S1C33210 except for details of the peripheral circuits. S1C33210 FUNCTION PART Describes details of all the peripheral circuit blocks for the S1C33 Family microcomputers. Refer to the " S1C33 000 Core CPU Manual " for detail s of the S1C330 00 32-bit RISC CPU .
TABLE OF CONTENTS S1C33210 PRODUCT PART Table of Contents 1 Outline..................................................................................................................... A-1 1.1 Features...............................................................................................................................................................A-1 1.2 Block Diagram .................................................................................................................................
TABLE OF CONTENTS Appendix A External Device Interface Timings......................................A-92 A.1 A.2 A.3 A.4 A.5 A.6 DRAM (70ns)....................................................................................................................................................A-93 DRAM (60ns)....................................................................................................................................................A-96 ROM and Burst ROM........................
TABLE OF CONTENTS S1C33210 FUNCTION PART Table of Contents I OUTLINE I-1 INTRODUCTION ............................................................................................... B-I-1-1 I-2 BLOCK DIAGRAM ............................................................................................ B-I-2-1 I-3 LIST OF PINS ................................................................................................... B-I-3-1 List of External I/O Pins..................................................
TABLE OF CONTENTS Bus Speed Mode ...............................................................................................................................B-II-4-17 Bus Clock Output ...............................................................................................................................B-II-4-17 Bus Cycles in External System Interface ................................................................................................B-II-4-18 SRAM Read Cycles.........................
TABLE OF CONTENTS III PERIPHERAL BLOCK III-1 INTRODUCTION ............................................................................................ B-III-1-1 III-2 PRESCALER ................................................................................................. B-III-2-1 Configuration of Prescaler..............................................................................................................................B-III-2-1 Source Clock....................................................
TABLE OF CONTENTS III-7 CLOCK TIMER ...............................................................................................B-III-7-1 Configuration of Clock Timer.........................................................................................................................B-III-7-1 Control and Operation of the Clock Timer ...............................................................................................B-III-7-2 Interrupt Function ..............................................
TABLE OF CONTENTS Overview...............................................................................................................................................B-III-10-8 PDC Communications Control and Operation....................................................................B-III-10-10 PHS Communications Mode....................................................................................................................B-III-10-11 PHS Communications Control and Operation....................
TABLE OF CONTENTS IV ANALOG BLOCK IV-1 INTRODUCTION............................................................................................ B-IV-1-1 IV-2 A/D CONVERTER.......................................................................................... B-IV-2-1 Features and Structure of A/D Converter ................................................................................................B-IV-2-1 I/O Pins of A/D Converter .....................................................................
S1C33210 PRODUCT PART
1 OUTLINE 1 Outline The S1C33210 is a Seiko Epson original 32-bit microcomputer. It features high speed, low power consumption, and low-voltage operation, and is ideal for portable products that require high-speed data processing. The S1C33210 consists of an S1C33000 32-bit RISC type CPU as its core, peripheral circuits including a bus control unit, DMA controller, interrupt controller, timers, serial interface, and A/D converter, and also mobile access interface and RAM.
1 OUTLINE General-purpose input and output ports: Shared with the I/O pins for internal peripheral circuits Input port 7 bits I/O port 27 bits One PHS, PDC, and HDLC channel each Mobile access interfaces External bus interface BCU (bus control unit) built-in • 24-bit address bus (internal 28-bit processing) • 16-bit data bus Data size is selectable from 8 bits and 16 bits in each area. • Little-endian memory access; big-endian may be set in each area.
1 OUTLINE 1.
1 OUTLINE 1.3 Pin Description 1.3.1 Pin Layout Diagram (plastic package) QFP15-128pin 96 65 97 64 INDEX 128 33 1 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin name P26/TM4/SOUT2 P27/TM5/SIN2 VSS BCLK P00/SIN0 P01/SOUT0 D15 VDD P03/#SRDY0 D14 P31/#BUSGET/#GARD D13 P32/#DMAACK0 D12 P33/#DMAACK1 D11 P02/#SCLK0 D10 K50/#DMAREQ0 #WRL/#WR/#WE #WRH/#BSH VSS K51/#DMAREQ1 #RD D9 D8 VDD K63/AD3 K62/AD2 AVDD K61/AD1 K60/AD0 No.
1 OUTLINE 1.3.2 Pin Functions Table 1.3.1 List of Pins for Power Supply System Pin name Pin No. I/O Pull-up Function QFP15-128 V DD 8, 27, 47, 74, 93, 111 – V SS 3, 22, 39, 54, 67, 90, 102, 104 – 30 – AVDD – Power supply (+) (104 Power supply (-); GND Pulldown) – Analog system power supply (+); AVDD = V DD Table 1.3.2 List of Pins for External Bus Interface Signals Pin name Pin No.
1 OUTLINE Pin name Pin No. I/O Pull-up Function O – #CE4: QFP15-128 #CE4 #CE11 #CE11&12 35 Area 4 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00" (default) #CE11: Area 11 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01" * When CEFUNC[1:0] = "1x", this pin outputs #CE11+#CE12 signal.
1 OUTLINE Table 1.3.3 List of Pins for HSDMA Control Signals Pin name Pin No. I/O Pull-up Function QFP15-128 K50 #DMAREQ0 19 I Pull-up K50: Input port when CFK50(D0/0x402C0) = "0" (default) #DMAREQ0: HSDMA Ch. 0 request input when CFK50(D0/0x402C0) = "1" K51 #DMAREQ1 23 I Pull-up K51: Input port when CFK51(D1/0x402C0) = "0" (default) #DMAREQ1: HSDMA Ch.
1 OUTLINE Table 1.3.4 List of Pins for Internal Peripheral Circuits Pin name Pin No. I/O Pull-up Function QFP15-128 K52 #ADTRG 33 I Pull-up K52: #ADTRG: K60 AD0 32 I – K60: AD0: Input port when CFK60(D0/0x402C3) = "0" (default) A/D converter Ch. 0 input when CFK60(D0/0x402C3) = "1" K61 AD1 31 I – K61: AD1: Input port when CFK61(D1/0x402C3) = "0" (default) A/D converter Ch.
1 OUTLINE Pin name Pin No.
1 OUTLINE Pin name Pin No.
2 POWER SUPPLY 2 Power Supply This chapter explains the operating voltage of the S1C33210. 2.1 Power Supply Pins The S1C33210 has the power supply pins shown in Table 2.1.1. Pin name VDD VSS AV DD Table 2.1.1 Power Supply Pins Pin No. Function QFP15-128 8, 27, 47, 74, 93, 111 Power supply (+) 3, 22, 39, 54, 67, 90, Power supply (-); GND 102, 104 30 Analog system power supply (+); AV DD = VDD 2.7 to 3.6 V VDD CPU core Internal peripheral circuit I/O interface circuit 2.7 to 3.
2 POWER SUPPLY 2.3 Power Supply for Analog Circuits (AVDD) The analog power supply pin (AVDD) is provided separately from the VDD and VDD pins in order that the digital circuits do not affect the analog circuit (A/D converter). The AVDD pin is used to supply an analog power voltage and the VSS pin is used as the analog ground. Supply the same voltage level as the VDD to the AVDD pin. AVDD = VDD, VSS = GND Note: Be sure to supply VDD to the AVDD pin even if the analog circuit is not used.
3 INTERNAL MEMORY 3 Internal Memory This chapter explains the internal memory configuration. Figure 3.1 shows the S1C33210 memory map.
4 PERIPHERAL CIRCUITS 4 Peripheral Circuits This chapter lists the built-in peripheral circuits and the I/O memory map. For details of the circuits, refer to the "S1C33210 FUNCTION PART". 4.1 List of Peripheral Circuits The S1C33210 consists of the C33 Core Block, C33 Peripheral Block, C33 DMA Block and C33 Analog Block.
4 PERIPHERAL CIRCUITS 4.2 I/O Memory Map Table 4.2.
4 PERIPHERAL CIRCUITS Register name Address Bit Name Function 16-bit timer 3 clock control register 004014A D7–4 – (B) D3 P16TON3 D2 P16TS32 D1 P16TS31 D0 P16TS30 reserved 16-bit timer 3 clock control 16-bit timer 3 clock division ratio selection 16-bit timer 4 clock control register 004014B D7–4 – (B) D3 P16TON4 D2 P16TS42 D1 P16TS41 D0 P16TS40 reserved 16-bit timer 4 clock control 16-bit timer 4 clock division ratio selection 16-bit timer 5 clock control register 004014C D7–4 – (B) D3 P16TON5
4 PERIPHERAL CIRCUITS Register name Address Bit Name 8-bit timer 2/3 clock control register D7 D6 D5 D4 P8TON3 P8TS32 P8TS31 P8TS30 004014E (B) D3 D2 D1 D0 P8TON2 P8TS22 P8TS21 P8TS20 A/D clock 004014F control register (B) D7–4 D3 D2 D1 D0 Clock timer Run/Stop register D7–2 – D1 TCRST D0 TCRUN 0040151 (B) Clock timer 0040152 interrupt (B) control register Clock timer 0040153 divider register (B) Clock timer second register 0040154 (B) – PSONAD PSAD2 PSAD1 PSAD0 Function 8-bit timer 3 clo
4 PERIPHERAL CIRCUITS Register name Address Bit Clock timer 0040155 minute register (B) D7–6 D5 D4 D3 D2 D1 D0 – TCHD5 TCHD4 TCHD3 TCHD2 TCHD1 TCHD0 reserved Clock timer minute counter data TCHD5 = MSB TCHD0 = LSB Clock timer hour register D7–5 D4 D3 D2 D1 D0 – TCDD4 TCDD3 TCDD2 TCDD1 TCDD0 Clock timer 0040157 day (low-order) (B) register D7 D6 D5 D4 D3 D2 D1 D0 Clock timer day (highorder) register 0040158 (B) Clock timer minute comparison register 0040159 (B) Clock timer hour comparison reg
4 PERIPHERAL CIRCUITS Register name Address Bit 8-bit timer 0 0040160 control register (B) D7–3 D2 D1 D0 Name Function – PTOUT0 PSET0 PTRUN0 reserved 8-bit timer 0 clock output control 8-bit timer 0 preset 8-bit timer 0 Run/Stop control Setting – 1 On 1 Preset 1 Run 0 Off 0 Invalid 0 Stop Init. R/W Remarks – 0 – 0 – 0 when being read. R/W W 0 when being read.
4 PERIPHERAL CIRCUITS Register name Address Bit Name Function 8-bit timer 3 004016C D7–3 – control register (B) D2 PTOUT3 D1 PSET3 D0 PTRUN3 reserved 8-bit timer 3 clock output control 8-bit timer 3 preset 8-bit timer 3 Run/Stop control 8-bit timer 3 reload data register 004016D (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD37 RLD36 RLD35 RLD34 RLD33 RLD32 RLD31 RLD30 8-bit timer 3 reload data RLD37 = MSB RLD30 = LSB 8-bit timer 3 counter data register 004016E (B) D7 D6 D5 D4 D3 D2 D1 D0 PTD37 PTD36 PTD35 P
4 PERIPHERAL CIRCUITS Register name Address Bit Name Function Setting Init. R/W Remarks Watchdog 0040170 timer write(B) protect register D7 WRWD D6–0 – EWD write protection – 1 Write enabled 0 Write-protect – 0 – R/W – 0 when being read. Watchdog timer enable register D7–2 – D1 EWD D0 – – Watchdog timer enable – – 1 NMI enabled 0 NMI disabled – – 0 – – 0 when being read. R/W – 0 when being read.
4 PERIPHERAL CIRCUITS Register name Address Bit Name Power control register D7 D6 CLKDT1 CLKDT0 System clock division ratio selection D5 D4–3 D2 D1 D0 PSCON – CLKCHG SOSC3 SOSC1 Prescaler On/Off control reserved 1 OSC3 CPU operating clock switch High-speed (OSC3) oscillation On/Off 1 On Low-speed (OSC1) oscillation On/Off 1 On 0040180 (B) Function Setting CLKDT[1:0] 1 1 1 0 0 1 0 0 1 On R/W 1 0 1 1 1 R/W – Writing 1 not allowed. R/W R/W R/W – 0 0 – R/W – 0 1 0 0 – 0 when being read.
4 PERIPHERAL CIRCUITS Register name Address Bit Serial I/F Ch.0 transmit data register 00401E0 (B) D7 D6 D5 D4 D3 D2 D1 D0 TXD07 TXD06 TXD05 TXD04 TXD03 TXD02 TXD01 TXD00 Name Serial I/F Ch.0 transmit data TXD07(06) = MSB TXD00 = LSB Function 0x0 to 0xFF(0x7F) X X X X X X X X Serial I/F Ch.0 receive data register 00401E1 (B) D7 D6 D5 D4 D3 D2 D1 D0 RXD07 RXD06 RXD05 RXD04 RXD03 RXD02 RXD01 RXD00 Serial I/F Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit Serial I/F Ch.1 transmit data register 00401E5 (B) D7 D6 D5 D4 D3 D2 D1 D0 TXD17 TXD16 TXD15 TXD14 TXD13 TXD12 TXD11 TXD10 Name Serial I/F Ch.1 transmit data TXD17(16) = MSB TXD10 = LSB Function 0x0 to 0xFF(0x7F) X X X X X X X X Serial I/F Ch.1 receive data register 00401E6 (B) D7 D6 D5 D4 D3 D2 D1 D0 RXD17 RXD16 RXD15 RXD14 RXD13 RXD12 RXD11 RXD10 Serial I/F Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit Serial I/F Ch.2 00401F3 control register (B) D7 D6 D5 D4 D3 D2 D1 D0 TXEN2 RXEN2 EPR2 PMD2 STPB2 SSCK2 SMD21 SMD20 Name Ch.2 transmit enable Ch.2 receive enable Ch.2 parity enable Ch.2 parity mode selection Ch.2 stop bit selection Ch.2 input clock selection Ch.2 transfer mode selection Function – DIVMD2 IRTL2 IRRL2 IRMD21 IRMD20 reserved Ch.2 async. clock division ratio Ch.2 IrDA I/F output logic inversion Ch.2 IrDA I/F input logic inversion Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit A/D conversion 0040240 result (low(B) order) register D7 D6 D5 D4 D3 D2 D1 D0 Name ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 Function 0 0 0 0 0 0 0 0 R – 0x0 to 0x3FF (high-order 2 bits) – 0 0 – R – – 0 0 0 D7–2 – D1 ADD9 D0 ADD8 – A/D converted data (high-order 2 bits) ADD9 = MSB A/D trigger register D7–6 D5 D4 D3 – MS TS1 TS0 – A/D conversion mode selection A/D conversion trigger selection D2 D1 D0 CH2 CH1 CH0 A/D conversion channel statu
4 PERIPHERAL CIRCUITS Register name Address Bit Port input 0/1 0040260 interrupt (B) priority register D7 D6 D5 D4 D3 D2 D1 D0 – PP1L2 PP1L1 PP1L0 – PP0L2 PP0L1 PP0L0 reserved Port input 1 interrupt level – 0 to 7 reserved Port input 0 interrupt level – 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 – PP3L2 PP3L1 PP3L0 – PP2L2 PP2L1 PP2L0 reserved Port input 3 interrupt level – 0 to 7 reserved Port input 2 interrupt level – 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 – PK1L2 PK1L1 PK1L0 – PK0L2 PK0L1 PK0L0 reserved Ke
4 PERIPHERAL CIRCUITS Register name Address Bit 8-bit timer, 0040269 serial I/F Ch.0 (B) interrupt priority register D7 D6 D5 D4 D3 D2 D1 D0 – PSIO02 PSIO01 PSIO00 – P8TM2 P8TM1 P8TM0 reserved Serial interface Ch.0 interrupt level – 0 to 7 reserved 8-bit timer 0–3 interrupt level – 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 – PAD2 PAD1 PAD0 – PSIO12 PSIO11 PSIO10 reserved A/D converter interrupt level – 0 to 7 reserved Serial interface Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit Key input, 0040270 port input 0–3 (B) interrupt enable register D7–6 D5 D4 D3 D2 D1 D0 – EK1 EK0 EP3 EP2 EP1 EP0 Name reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 Function DMA interrupt 0040271 enable register (B) D7–5 D4 D3 D2 D1 D0 – EIDMA EHDM3 EHDM2 EHDM1 EHDM0 reserved IDMA High-speed DMA Ch.3 High-speed DMA Ch.2 High-speed DMA Ch.1 High-speed DMA Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit Key input, 0040280 port input 0–3 (B) interrupt factor flag register D7–6 D5 D4 D3 D2 D1 D0 – FK1 FK0 FP3 FP2 FP1 FP0 Name reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 Function DMA interrupt factor flag register 0040281 (B) D7–5 D4 D3 D2 D1 D0 – FIDMA FHDM3 FHDM2 FHDM1 FHDM0 reserved IDMA High-speed DMA Ch.3 High-speed DMA Ch.2 High-speed DMA Ch.1 High-speed DMA Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit Name Port input 0–3, high-speed DMA Ch. 0/1, 16-bit timer 0 IDMA request register 0040290 (B) D7 D6 D5 D4 D3 D2 D1 D0 R16TC0 R16TU0 RHDM1 RHDM0 RP3 RP2 RP1 RP0 16-bit timer 0 comparison A 16-bit timer 0 comparison B High-speed DMA Ch.1 High-speed DMA Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit Name High-speed DMA Ch.0/1 trigger set-up register D7 D6 D5 D4 HSD1S3 HSD1S2 HSD1S1 HSD1S0 High-speed DMA Ch.1 trigger set-up D3 D2 D1 D0 HSD0S3 HSD0S2 HSD0S1 HSD0S0 High-speed DMA Ch.0 trigger set-up D7 D6 D5 D4 HSD3S3 HSD3S2 HSD3S1 HSD3S0 High-speed DMA Ch.3 trigger set-up D3 D2 D1 D0 HSD2S3 HSD2S2 HSD2S1 HSD2S0 High-speed DMA Ch.2 trigger set-up High-speed DMA Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit Name Function K5 function select register 00402C0 D7–4 – (B) D3 CP4 D2 CFK52 D1 CFK51 D0 CFK50 reserved CP4 K52 function selection K51 function selection K50 function selection K5 input port data register 00402C1 D7–5 – (B) D4 – D3 CP4D D2 K52D D1 K51D D0 K50D reserved – CP4 data K52 input port data K51 input port data K50 input port data K6 function select register 00402C3 (B) D7 D6 D5 D4 D3 D2 D1 D0 CP3 CP2 CP1 CP0 CFK63 CFK62 CFK61 CFK60 K6 i
4 PERIPHERAL CIRCUITS Register name Address Bit Interrupt factor 00402C5 FP function switching register D7 D6 T8CH5S0 SIO3TS0 8-bit timer 5 underflow SIO Ch.3 transmit buffer empty D5 D4 T8CH4S0 SIO3RS0 8-bit timer 4 underflow SIO Ch.3 receive buffer full D3 SIO2TS0 SIO Ch.2 transmit buffer empty D2 SIO3ES0 SIO Ch.3 receive error D1 SIO2RS0 SIO Ch.2 receive buffer full D0 SIO2ES0 SIO Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit Name Function Key input interrupt (FPK0) input comparison register 00402CC D7–5 – (B) D4 SCPK04 D3 SCPK03 D2 SCPK02 D1 SCPK01 D0 SCPK00 reserved FPK04 input comparison FPK03 input comparison FPK02 input comparison FPK01 input comparison FPK00 input comparison Key input interrupt (FPK1) input comparison register 00402CD D7–4 – (B) D3 SCPK13 D2 SCPK12 D1 SCPK11 D0 SCPK10 reserved FPK13 input comparison FPK12 input comparison FPK11 input comparison FPK1
4 PERIPHERAL CIRCUITS Register name Address Bit P1 I/O control register 00402D6 (B) D7 D6 D5 D4 D3 D2 D1 D0 Port SIO function extension register 00402D7 D7–4 – D3 CFP322 reserved P32 function selection 2 1 – D2 CFP152 P15 function selection 2 1 – D1 CFP162 P16 function selection 2 1 – D0 CFP332 P33 function selection 2 1 – 00402D8 (B) D7 D6 D5 D4 D3 D2 D1 D0 CFP27 CFP26 CFP25 CFP24 CFP23 CFP22 CFP21 CFP20 P27 function selection P26 function selection P25 function selection P24 f
4 PERIPHERAL CIRCUITS Register name Address Port function extension register 00402DF (B) Areas 18–15 0048120 set-up register (HW) Areas 14–13 0048122 set-up register (HW) Bit Name Function D7-6 D5 D4 D3 D2 D1 – CFEX5 CFEX4 CFEX3 CFEX2 CFEX1 reserved P05 port extended function P04 port extended function P31 port extended function P21 port extended function P10, P11, P13 port extended function D0 CFEX0 P12, P14 port extended function DF DE DD DC – A18SZ A18DF1 A18DF0 DB DA D9 D8 – A18WT2 A18W
4 PERIPHERAL CIRCUITS Register name Address Bit Areas 12–11 0048124 set-up register (HW) DF–7 D6 D5 D4 – A12SZ A12DF1 A12DF0 D3 D2 D1 D0 – A12WT2 A12WT1 A12WT0 Areas 10–9 0048126 set-up register (HW) Areas 8–7 0048128 set-up register (HW) A-38 Name DF-B – DA A10BW1 D9 A10BW0 Function Setting Init. R/W Remarks reserved – Areas 12–11 device size selection 1 8 bits 0 16 bits Areas 12–11 A18DF[1:0] Number of cycles 1 1 3.5 output disable delay time 1 0 2.5 0 1 1.5 0 0 0.
4 PERIPHERAL CIRCUITS Register name Address Bit Name Areas 6–4 004812A DF–E – set-up register (HW) DD A6DF1 DC A6DF0 Function reserved Area 6 output disable delay time Setting – A6DF[1:0] Number of cycles 1 1 3.5 1 0 2.5 0 1 1.5 0 0 0.5 – A6WT[2:0] Wait cycles 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 – 1 8 bits 0 16 bits A5DF[1:0] Number of cycles 1 1 3.5 1 0 2.5 0 1 1.5 0 0 0.5 Init. R/W Remarks – 1 1 – 0 when being read. R/W – 1 1 1 – 0 when being read.
4 PERIPHERAL CIRCUITS Register name Address Bit Name Function DRAM timing 0048130 DF–C – reserved set-up register (HW) DB – reserved DA CEFUNC1 #CE pin function selection D9 CEFUNC0 Setting – – CFFUNC[1:0] #CE output 1 x #CE7/8..#CE17/18 #CE6..#CE17 0 1 #CE4..#CE10 0 0 1 Successive 0 Normal RPRC[1:0] Number of cycles 1 1 4 1 0 3 0 1 2 0 0 1 – CASC[1:0] Number of cycles 1 1 4 1 0 3 0 1 2 0 0 1 – RASC[1:0] Number of cycles 1 1 4 1 0 3 0 1 2 0 0 1 Init. R/W Remarks – – 0 0 – 0 when being read.
4 PERIPHERAL CIRCUITS Register name Address Bit G/A read signal 0048138 control register (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BCLK select register Name A18AS A16AS A14AS A12AS – A8AS A6AS A5AS A18RD A16RD A14RD A12RD – A8RD A6RD A5RD 004813A D7–4 – (B) D3 A1X1MD D2 – D1 BCLKSEL1 D0 BCLKSEL0 S1C33210 PRODUCT PART Function Area 18, 17 address strobe signal Area 16, 15 address strobe signal Area 14, 13 address strobe signal Area 12, 11 address strobe signal reserved Area 8, 7 address s
4 PERIPHERAL CIRCUITS Register name Address Bit Name Function Setting 16-bit timer 0 comparison register A 0048180 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR0A15 CR0A14 CR0A13 CR0A12 CR0A11 CR0A10 CR0A9 CR0A8 CR0A7 CR0A6 CR0A5 CR0A4 CR0A3 CR0A2 CR0A1 CR0A0 16-bit timer 0 comparison data A CR0A15 = MSB CR0A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 0 comparison register B 0048182 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR0B15 CR0B14 CR0B13 C
4 PERIPHERAL CIRCUITS Register name Address Bit Name Function Setting 16-bit timer 1 comparison register A 0048188 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR1A15 CR1A14 CR1A13 CR1A12 CR1A11 CR1A10 CR1A9 CR1A8 CR1A7 CR1A6 CR1A5 CR1A4 CR1A3 CR1A2 CR1A1 CR1A0 16-bit timer 1 comparison data A CR1A15 = MSB CR1A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 1 comparison register B 004818A (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR1B15 CR1B14 CR1B13 C
4 PERIPHERAL CIRCUITS Register name Address Bit Name Function Setting 16-bit timer 2 comparison register A 0048190 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR2A15 CR2A14 CR2A13 CR2A12 CR2A11 CR2A10 CR2A9 CR2A8 CR2A7 CR2A6 CR2A5 CR2A4 CR2A3 CR2A2 CR2A1 CR2A0 16-bit timer 2 comparison data A CR2A15 = MSB CR2A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 2 comparison register B 0048192 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR2B15 CR2B14 CR2B13 C
4 PERIPHERAL CIRCUITS Register name Address Bit Name Function Setting 16-bit timer 3 comparison register A 0048198 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR3A15 CR3A14 CR3A13 CR3A12 CR3A11 CR3A10 CR3A9 CR3A8 CR3A7 CR3A6 CR3A5 CR3A4 CR3A3 CR3A2 CR3A1 CR3A0 16-bit timer 3 comparison data A CR3A15 = MSB CR3A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 3 comparison register B 004819A (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR3B15 CR3B14 CR3B13 C
4 PERIPHERAL CIRCUITS Register name Address Bit Name Function Setting 16-bit timer 4 comparison register A 00481A0 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR4A15 CR4A14 CR4A13 CR4A12 CR4A11 CR4A10 CR4A9 CR4A8 CR4A7 CR4A6 CR4A5 CR4A4 CR4A3 CR4A2 CR4A1 CR4A0 16-bit timer 4 comparison data A CR4A15 = MSB CR4A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 4 comparison register B 00481A2 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR4B15 CR4B14 CR4B13 C
4 PERIPHERAL CIRCUITS Register name Address Bit Name Function Setting 16-bit timer 5 comparison register A 00481A8 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR5A15 CR5A14 CR5A13 CR5A12 CR5A11 CR5A10 CR5A9 CR5A8 CR5A7 CR5A6 CR5A5 CR5A4 CR5A3 CR5A2 CR5A1 CR5A0 16-bit timer 5 comparison data A CR5A15 = MSB CR5A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 5 comparison register B 00481AA (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR5B15 CR5B14 CR5B13 C
4 PERIPHERAL CIRCUITS Register name Address Bit IDMA base address loworder register 0048200 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IDMA base address high-order register 0048202 DF–C – (HW) DB DBASEH11 DA DBASEH10 D9 DBASEH9 D8 DBASEH8 D7 DBASEH7 D6 DBASEH6 D5 DBASEH5 D4 DBASEH4 D3 DBASEH3 D2 DBASEH2 D1 DBASEH1 D0 DBASEH0 reserved IDMA base address high-order 12 bits (Initial value: 0x0C003A0) IDMA start register 0048204 (B) D7 DSTART D6–0 DCHN IDMA start IDMA channel number 1 IDMA
4 PERIPHERAL CIRCUITS Register name Address Bit Name High-speed DMA Ch.0 transfer counter register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC0_L7 TC0_L6 TC0_L5 TC0_L4 TC0_L3 TC0_L2 TC0_L1 TC0_L0 BLKLEN07 BLKLEN06 BLKLEN05 BLKLEN04 BLKLEN03 BLKLEN02 BLKLEN01 BLKLEN00 Ch.0 transfer counter[7:0] (block transfer mode) DF DE DUALM0 D0DIR DD–8 D7 D6 D5 D4 D3 D2 D1 D0 – TC0_H7 TC0_H6 TC0_H5 TC0_H4 TC0_H3 TC0_H2 TC0_H1 TC0_H0 Ch.0 address mode selection D) Invalid S) Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit High-speed 0048228 DMA Ch.0 (HW) low-order destination address set-up register DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 D0ADRL15 D) Ch.0 destination address[15:0] D0ADRL14 S) Invalid D0ADRL13 D0ADRL12 D0ADRL11 D0ADRL10 D0ADRL9 D0ADRL8 D0ADRL7 D0ADRL6 D0ADRL5 D0ADRL4 D0ADRL3 D0ADRL2 D0ADRL1 D0ADRL0 DF DE D0MOD1 D0MOD0 Ch.0 transfer mode DD DC D0IN1 D0IN0 D) Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit Name High-speed DMA Ch.1 transfer counter register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC1_L7 TC1_L6 TC1_L5 TC1_L4 TC1_L3 TC1_L2 TC1_L1 TC1_L0 BLKLEN17 BLKLEN16 BLKLEN15 BLKLEN14 BLKLEN13 BLKLEN12 BLKLEN11 BLKLEN10 Ch.1 transfer counter[7:0] (block transfer mode) DF DE DUALM1 D1DIR DD–8 D7 D6 D5 D4 D3 D2 D1 D0 – TC1_H7 TC1_H6 TC1_H5 TC1_H4 TC1_H3 TC1_H2 TC1_H1 TC1_H0 Ch.1 address mode selection D) Invalid S) Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit High-speed 0048238 DMA Ch.1 (HW) low-order destination address set-up register DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 D1ADRL15 D) Ch.1 destination address[15:0] D1ADRL14 S) Invalid D1ADRL13 D1ADRL12 D1ADRL11 D1ADRL10 D1ADRL9 D1ADRL8 D1ADRL7 D1ADRL6 D1ADRL5 D1ADRL4 D1ADRL3 D1ADRL2 D1ADRL1 D1ADRL0 DF DE D1MOD1 D1MOD0 Ch.1 transfer mode DD DC D1IN1 D1IN0 D) Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit Name High-speed DMA Ch.2 transfer counter register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC2_L7 TC2_L6 TC2_L5 TC2_L4 TC2_L3 TC2_L2 TC2_L1 TC2_L0 BLKLEN27 BLKLEN26 BLKLEN25 BLKLEN24 BLKLEN23 BLKLEN22 BLKLEN21 BLKLEN20 Ch.2 transfer counter[7:0] (block transfer mode) DF DE DUALM2 D2DIR DD–8 D7 D6 D5 D4 D3 D2 D1 D0 – TC2_H7 TC2_H6 TC2_H5 TC2_H4 TC2_H3 TC2_H2 TC2_H1 TC2_H0 Ch.2 address mode selection D) Invalid S) Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit High-speed 0048248 DMA Ch.2 (HW) low-order destination address set-up register DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 D2ADRL15 D) Ch.2 destination address[15:0] D2ADRL14 S) Invalid D2ADRL13 D2ADRL12 D2ADRL11 D2ADRL10 D2ADRL9 D2ADRL8 D2ADRL7 D2ADRL6 D2ADRL5 D2ADRL4 D2ADRL3 D2ADRL2 D2ADRL1 D2ADRL0 DF DE D2MOD1 D2MOD0 Ch.2 transfer mode DD DC D2IN1 D2IN0 D) Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit Name High-speed DMA Ch.3 transfer counter register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC3_L7 TC3_L6 TC3_L5 TC3_L4 TC3_L3 TC3_L2 TC3_L1 TC3_L0 BLKLEN37 BLKLEN36 BLKLEN35 BLKLEN34 BLKLEN33 BLKLEN32 BLKLEN31 BLKLEN30 Ch.3 transfer counter[7:0] (block transfer mode) DF DE DUALM3 D3DIR DD–8 D7 D6 D5 D4 D3 D2 D1 D0 – TC3_H7 TC3_H6 TC3_H5 TC3_H4 TC3_H3 TC3_H2 TC3_H1 TC3_H0 Ch.3 address mode selection D) Invalid S) Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit High-speed 0048258 DMA Ch.3 (HW) low-order destination address set-up register DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 D3ADRL15 D) Ch.3 destination address[15:0] D3ADRL14 S) Invalid D3ADRL13 D3ADRL12 D3ADRL11 D3ADRL10 D3ADRL9 D3ADRL8 D3ADRL7 D3ADRL6 D3ADRL5 D3ADRL4 D3ADRL3 D3ADRL2 D3ADRL1 D3ADRL0 DF DE D3MOD1 D3MOD0 Ch.3 transfer mode DD DC D3IN1 D3IN0 D) Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit Name Function Setting Communications 0200000 D15–2 – macro select (HW) D1 MCRS1 register D0 MCRS0 – Master configuration selection Software reset register – Reset PHS communications block 1 Reset Reset PDC communications block 1 Reset Reset HDLC communications block 1 Reset – – Specify clock frequency divider for communications block – 0200002 D15–3 – (HW) D2 PHSRST D1 PDCRST D0 HDLRST Communications 0200004 D15-4 – block clock (HW) D3 CKD3 frequ
4 PERIPHERAL CIRCUITS Register name Address Bit Name Function Setting Communications 0200028 D15–5 – block CP4 (HW) D4 CP4EN4 interrupt select D3 CP4EN3 register D2 CP4EN2 D1 CP4EN1 D0 CP4EN0 – Map UINT4 interrupt requests to CP4 Map UINT3 interrupt requests to CP4 Map UINT2 interrupt requests to CP4 Map UINT1 interrupt requests to CP4 Map UINT0 interrupt requests to CP4 1 1 1 1 1 Enable Enable Enable Enable Enable Communications 020002A D15–12 – D11 RI block modem (HW) D10 CTS status register D9
4 PERIPHERAL CIRCUITS Register name Address Bit Name Function HDLC interrupt 0200302 D15–8 – control register (HW) D7 ERES D6 RESINT D5–2 – D1 RRXINT D0 RTXINT – HDLC error reset HDLC E/S interrupt reset – HDLC receive interrupt reset HDLC transmit interrupt reset HDLC interrupt 0200304 D15–8 – enable settings (HW) D7 ABRTIES register D6 TXUEIES D5 HUNTIES D4 IDLDIES D3–0 – – Enable Abort interrupt setting Enable TXUDR interrupt setting Enable Hunt interrupt setting Enable idle detection interrupt s
4 PERIPHERAL CIRCUITS Register name Address Bit Name Function Setting Init.
4 PERIPHERAL CIRCUITS Register name Address HDLC residue code register Bit Name 0200332 D15–8 – (HW) D7 RCODE7 D6 RCODE6 D5 RCODE5 D4 RCODE4 D3 RCODE3 D2 RCODE2 D1 RCODE1 D0 RCODE0 Function Setting Init. R/W Remarks – RCODE[7:0] Residue Code 11111110 Number of valid bits in excess residue code bits at end of frame 11111100 11111000 11110000 11100000 11000000 10000000 – Effective bits 7 6 5 4 3 2 1 – X X X X X X X X – R 0 when being read.
5 POWER-DOWN CONTROL 5 Power-Down Control This chapter describes the controls used to reduce power consumption of the device. Points on power saving The current consumption of the device varies greatly with the CPU's operation mode, the system clocks used, and the peripheral circuits operated.
5 POWER-DOWN CONTROL Switching over the system clocks Normally, the system is clocked by the high-speed (OSC3) oscillation clock. If high-speed operation is unnecessary, switch the system clock to the low-speed (OSC1) oscillation clock and turn off the high-speed (OSC3) oscillation circuit. This helps to reduce current consumption. However, if DRAM is connected directly to the device, note that the refresh function is also turned off.
5 POWER-DOWN CONTROL "1" "0" Prescaler ON/OFF Function PSCON(D5)/Power control register(0x40180) Control bit ON OFF ON 16-bit timer 0 clock control P16TON0(D3)/16-bit timer 0 clock control register(0x40147) ON OFF OFF RUN STOP STOP ON OFF OFF RUN STOP STOP 16-bit timer 0 Run/Stop PRUN0(D0)/16-bit timer 0 control register(0x48186) 16-bit timer 1 clock control P16TON1(D3)/16-bit timer 1 clock control register(0x40148) 16-bit timer 1 Run/Stop PRUN1(D0)/16-bit timer 1 control regist
6 BASIC EXTERNAL WIRING DIAGRAM 6 Basic External Wiring Diagram External Bus HSDMA Serial I/O A/D input Timer input/output A[23:0] D[15:0] #RD #DRD #GARD #GAAS #WRL/#WR/#WE #WRH/#BSH #DWR #HCAS #LCAS #CExx/#RASx #CE10EX #WAIT BCLK #BUSREQ #BUSACK #BUSGET S1C33210 #NMI [The potential of the substrate #DMAREQx (back of the chip) is VSS.
7 PRECAUTIONS ON MOUNTING 7 Precautions on Mounting The following shows the precautions when designing the board and mounting the IC. Oscillation Circuit • Oscillation characteristics change depending on conditions (board pattern, components used, etc.). In particular, when a ceramic oscillator or crystal oscillator is used, use the oscillator manufacturer's recommended values for constants such as capacitance and resistance. • Disturbances of the oscillation clock due to noise may cause a malfunction.
7 PRECAUTIONS ON MOUNTING (2) When connecting between the VDD and VSS pins with a bypass capacitor, the pins should be connected as short as possible. Bypass capacitor connection example VDD VDD VSS VSS A/D Converter • When the A/D converter is not used, the power supply pin AVDD for the analog system should be connected to VDDE.
8 ELECTRICAL CHARACTERISTICS 8 Electrical Characteristics 8.1 Absolute Maximum Rating Item Symbol Supply voltage Input voltage High-level output current VDD VI IOH Low-level output current IOL Analog power voltage Analog input voltage Storage temperature AV DDE AV IN TSTG A-68 Condition 1 pin Total of all pins 1 pin Total of all pins EPSON Rated value -0.3 to +4.0 -0.3 to VDDE +0.5 -10 -40 10 40 -0.3 to +7.0 -0.3 to AV DDE +0.
8 ELECTRICAL CHARACTERISTICS 8.2 Recommended Operating Conditions Item Supply voltage Input voltage CPU operating clock frequency Low-speed oscillation frequency Operating temperature Input rise time (normal input) Input fall time (normal input) Input rise time (schmitt input) Input fall time (schmitt input) S1C33210 PRODUCT PART Symbol Condition VDD VI fCPU fOSC1 Ta t ri t fi t ri t fi EPSON Min. Typ. Max. 2.70 VSS – – -40 – – – – – – – 32.768 25 – – – – 3.
8 ELECTRICAL CHARACTERISTICS 8.3 DC Characteristics Item Symbol (Unless otherwise specified: VDD =2.7V to 3.6V, Ta=-40°C to +85°C) Condition Min. Typ. Max. Unit ∗ -1 – 1 µA -1 – 1 µA IOH=-2mA (Type1), IOH=-6mA (Type2), VDD – – V -0.4 IOH=-12mA (Type3), V DD=Min. IOL =2mA (Type1), IOL =6mA (Type2), – – 0.
8 ELECTRICAL CHARACTERISTICS 8.4 Current Consumption Item (Unless otherwise specified: VDD =2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C) Condition Min. Typ. Max.
8 ELECTRICAL CHARACTERISTICS 8.5 A/D Converter Characteristics (Unless otherwise specified: AV DD =VDD =2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C, ST[1:0]=11) Symbol Condition Min. Typ. Max.
8 ELECTRICAL CHARACTERISTICS Integral linearity error 3FF Digital output (hex) 3FE V'[3FF]h 3FD Integral linearity error EL = VN' - VN [LSB] 1LSB' VN VN' 003 Actual conversion characteristic 002 Ideal conversion characteristic 001 V'[000]h 000 VSS Analog input AVDD Differential linearity error Digital output (hex) N+1 Ideal conversion characteristic N Actual conversion characteristic N-1 V'[N]h Differential linearity error ED = N-2 V'[N-1]h V'[N]h - V'[N-1]h - 1 [LSB] 1LSB' Analog input S1C
8 ELECTRICAL CHARACTERISTICS 8.6 AC Characteristics 8.6.1 Symbol Description tCYC: Bus-clock cycle time • In x1 mode, tCYC = 50 ns (20 MHz) when the CPU is operated with a 20-MHz clock tCYC = 30 ns (33 MHz) when the CPU is operated with a 33-MHz clock • In x2 mode, tCYC = 50 ns (20 MHz) when the CPU is operated with a 40-MHz clock tCYC = 40 ns (25 MHz) when the CPU is operated with a 50-MHz clock WC: Number of wait cycles Up to 7 cycles can be set for the number of cycles using the BCU control register.
8 ELECTRICAL CHARACTERISTICS 8.6.3 C33 Block AC Characteristic Tables External clock input characteristics (Note) These AC characteristics apply to input signals from outside the IC. The OSC3 input clock must be within VDD to VSS voltage range. Item High-speed clock cycle time OSC3 clock input duty OSC3 clock input rise time OSC3 clock input fall time BCLK high-level output delay time BCLK low-level output delay time Minimum reset pulse width (Unless otherwise specified: VDD =2.7V to 3.
8 ELECTRICAL CHARACTERISTICS Common characteristics Item Address delay time #CEx delay time (1) #CEx delay time (2) Wait setup time Wait hold time Read signal delay time (1) Read data setup time Read data hold time Write signal delay time (1) Write data delay time (1) Write data delay time (2) Write data hold time (Unless otherwise specified: VDD =2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C) Symbol Min. Max.
8 ELECTRICAL CHARACTERISTICS DRAM access cycle common characteristics Item #RAS signal delay time (1) #RAS signal delay time (2) #RAS signal pulse width #CAS signal delay time (1) #CAS signal delay time (2) #CAS signal pulse width Read signal delay time (3) Read signal pulse width (2) Write signal delay time (3) Write signal pulse width (2) (Unless otherwise specified: VDD =2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C) Symbol Min. Max.
8 ELECTRICAL CHARACTERISTICS 8.6.
8 ELECTRICAL CHARACTERISTICS SRAM read cycle (basic cycle: 1 cycle) tC3 BCLK ;;;; ;;;; t tAD tAD A[23:0] tCE1 CE2 #CEx tRDD1 tRDD2 tRDW #RD tCEAC1 tACC1 ;;;;;;; ;;;;;;; t t ;;;;;; ;;;;;; tRDAC1 D[15:0] ∗1 tRDH RDS ;;;;;; ;;;;;; #WAIT tWTS WTH *1 tRDH is measured with respect to the first signal change (negation) from among the #RD, #CEx and A[23:0] signals.
8 ELECTRICAL CHARACTERISTICS SRAM write cycle (basic cycle: 2 cycles) C1 C2 BCLK ;;;; ;;;; t tAD tAD A[23:0] tCE1 CE2 #CEx tWRD1 tWRD2 tWRW #WR tWDD1 tWDH D[15:0] t ;;;; ;;;; t ;;;;;; ;;;;;; WTS #WAIT WTH SRAM write cycle (when wait cycles are inserted) C1 Cw(wait cycle) Cw(wait cycle) Wait cycle follows Last cycle follows Cn(last cycle) BCLK ;;; ;;; t tAD tAD A[23:0] tCE1 CE2 #CEx tWRD1 tWRD2 tWRW #WR tWDD1 tWDH D[15:0] tWTS #WAIT A-80 t t ;;;;; ;;;;; WTH WTS t
8 ELECTRICAL CHARACTERISTICS DRAM random access cycle (basic cycle) Data transfer #1 RAS1 Next data transfer CAS1 PRE1(precharge) RAS1' CAS1' BCLK tAD ;;;;;;;;; ;;;;;;;;; t tAD tAD A[23:0] tRASD1 RASD2 tRASW #RAS tCASD1 tCASD2 tCASW #HCAS/ #LCAS tRDD1 tRDD3 tRDW2 #RD tCACF tRACF tACCF tRDS tRDH ∗1 ;;;;;;;;;; ;;;;;;;;;; t D[15:0] ;;;;; ;;;;; t WRD1 ;;;;;;; ;;;;;;; WRD3 tWRW2 #WE ;;;;; ;;;;; tWDD1 tWDD2 D[15:0] ∗1 tRDH is measured with respect to the first signal change (nega
8 ELECTRICAL CHARACTERISTICS EDO DRAM random access cycle (basic cycle) Data transfer #1 RAS1 Next data transfer CAS1 PRE1(precharge) RAS1' CAS1' BCLK tAD ;;;;;;;;; ;;;;;;;;; t tAD tAD A[23:0] tRASD1 RASD2 tRASW #RAS tCASD1 tCASD2 tCASW #HCAS/ #LCAS tRDD1 tRDD3 tRDW2 #RD tCACE tRACE tACCE tRDH ∗1 ;;;;;;;;;; ;;;;;;;;;; tRDS2 D[15:0] tWRD1 ;;; ;;; tWRD3 tWRW2 #WE ;;;;; ;;;;; tWDD1 tWDD2 D[15:0] ∗1 tRDH is measured with respect to the first signal change (negation) of either th
8 ELECTRICAL CHARACTERISTICS DRAM CAS-before-RAS refresh cycle CBR refresh cycle CCBR1 CCBR2 CCBR3 BCLK ;;;;;;;; ;;;;;;;; #RAS tRASD1 ;;;;;; ;;;;;; tRASD2 tCASD1 tCASD2 #HCAS/ #LCAS ;;;;;;;; ;;;;;;;; #WE ;;;;;; ;;;;;; DRAM self-refresh cycle Self-refresh mode setup Self-refresh mode Self-refresh mode canceration 6-cycle precharge (Fixed) BCLK #RAS ;;;;;;; ;;;;;;; tRASD1 ;;;; ;;;; tRASD2 tCASD1 tCASD2 #HCAS/ #LCAS Burst ROM read cycle SRAM read cycle Burst cycle Burst cycle Bur
8 ELECTRICAL CHARACTERISTICS #BUSREQ, #BUSACK and #NMI timing BCLK ;;; ;;; tBRQS #BUSREQ ;;;;; ;;;;; tBRQH Valid input tBAKD #BUSACK tZ2E eBUS_OUT signals ∗1 tB2Z eBUS_OUT signals ∗1 tNMIW #NMI ∗1 eBUS_OUT indicates the following pins: A[23:0], #RD, #WRL, #WRH, #HCAS, #LCAS, #CE[17:4], D[15:0] Input, output and I/O port timing BCLK ;;; ;;; tINPS Kxx, Pxx (input: data read from the port) ;;;;; ;;;;; tINPH Valid input tOUTD Pxx, Rxx (output) tKINW Kxx (K-port interrupt input) A-84 EPSON
8 ELECTRICAL CHARACTERISTICS 8.7 Oscillation Characteristics Oscillation characteristics change depending on conditions (board pattern, components used, etc.). Use the following characteristics as reference values. In particular, when a ceramic or crystal oscillator is used, use the oscillator manufacturer recommended values for constants such as capacitance and resistance. OSC1 crystal oscillation (Unless otherwise specified: crystal=Q11C02RX #1 32.
8 ELECTRICAL CHARACTERISTICS 8.8 PLL Characteristics Setting the PLLS0 and PLLS1 pins (recommended operating condition) VDD=2.7V to 3.6V PLLS1 PLLS0 Mode Fin (OSC3 clock) Fout 1 0 0 1 1 0 x2 x4 PLL not used 10 to 25MHz 10 to 12.5MHz – 20 to 50MHz 40 to 50MHz – PLL characteristics (Unless otherwise specified: VDD =2.7V to 3.6V, VSS=0V, crystal oscillator=Q3204DC #1, R1=4.7kΩ, C1=100pF, C2=5pF, Ta=-40°C to +85°C) Item Symbol Condition Min. Typ. Max.
9 PACKAGE 9 Package 9.1 Plastic Package QFP15-128pin (Unit: mm) 16±0.4 14±0.1 96 65 16±0.4 64 14±0.1 97 INDEX 128 33 1.4±0.1 32 0.4 +0.1 0.16 –0.05 +0.05 0.125–0.025 0° 10° 0.5±0.2 0.1 1.7max 1 1 Limit of power consumption The chip temperature of an LSI rises according to power consumption. The chip temperature can be calculated from environment temperature (Ta), thermal package resistance (θ) and power consumption (PD).
10 PAD LAYOUT 10 Pad Layout 10.1 Pad Layout Diagram Die No.
10 PAD LAYOUT 10.2 Pad Coordinate No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pad name P15/EXCL4/#DMAEND0 N.C. P26/TM4/SOUT2 P27/TM5/SIN2 VSS N.C. BCLK N.C. P00/SIN0 N.C. P01/SOUT0 N.C. D15 N.C. VDD N.C. P03/#SRDY0 N.C. D14 N.C. P31/#BUSGET/#GARD N.C. D13 N.C. P32/#DMAACK0 D12 P33/#DMAACK1 D11 P02/#SCLK0 D10 K50/#DMAREQ0 #WRL/#WR/#WE N.C. #WRH/#BSH N.C. VSS N.C. K51/#DMAREQ1 N.C. #RD N.C. D9 N.C. D8 N.C.
10 PAD LAYOUT No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Pad name N.C. P35/#BUSACK #HCAS #LCAS P34/#BUSREQ/#CE6 N.C. A4 A5 N.C. A6 A7 VSS N.C. P30/#WAIT/#CE4&5 N.C. A8 N.C. A9 N.C. #CE5/#CE15/#CE15&16 N.C. A10 N.C. A20 N.C. VDD N.C. A11 N.C. A21 N.C. P16/EXCL5/#DMAEND1 A12 A22 TST N.C. A13 A23 P04/SIN1 A14 N.C. A15 N.C. P05/SOUT1 N.C. A16 N.C.
10 No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 Pad name N.C. P23/TM1 N.C. DSIO N.C. P10/EXCL0/T8UF0/DST0 P11/EXCL1/T8UF1/DST1 N.C. P12/EXCL2/T8UF2/DST2 P13/EXCL3/T8UF3/DPC0 P14/FOSC1/DCLK P24/TM2/#SRDY2 N.C. P25/TM3/#SCLK2 N.C. N.C. X -2.834 -2.834 -2.834 -2.834 -2.834 -2.834 -2.834 -2.834 -2.834 -2.834 -2.834 -2.834 -2.834 -2.834 -2.834 -2.834 PAD LAYOUT Y -0.966 -1.05 -1.134 -1.218 -1.302 -1.386 -1.47 -1.554 -1.638 -1.722 -1.806 -1.89 -1.974 -2.058 2.154 -2.
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS Appendix A External Device Interface Timings This section shows setup examples for setting timing conditions of the external system interface as a reference material used when configuring a system with external devices. Pay attention to the following precautions when using this material. • The described AC characteristic values of external devices are standard values.
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS A.1 DRAM (70ns) DRAM interface setup examples – 70ns Operating frequency RAS precharge cycle RAS cycle CAS cycle 20MHz 25MHz 33MHz 2 2 2 1 1 2 2 2 3 Refresh RAS pulse Refresh RPC delay width 2 2 3 1 1 1 DRAM interface timing – 70ns DRAM interface Parameter Unit: ns 33MHz 25MHz 20MHz Symbol Min. Max.
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS DRAM: 70ns, CPU: 33MHz, random read/write cycle tRC RAS cycle CAS cycle RAS precharge 2 3 2 ROW #1 COL #1 ;;;;;;;;; ;;;;;;;;; BCLK A[11:0] tRAD tRAH tASC tRAS tASR ROW #2 tRP #RAS tRCD tCAS #CAS #RD tRAC tOAC tAA tCAC tOFF ;;;;;;;;; ;;;;;;;;; t D[15:0](RD) RD data ;;;; ;;;; WP #WE tDS tDH D[15:0](WR) ;;; ;;; WR data DRAM: 70ns, CPU: 33MHz, page-mode read/write cycle tPC RAS cycle CAS cycle CAS cycle RAS precharge
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS DRAM: 70ns, CPU: 25/20MHz, random read/write cycle RAS cycle CAS cycle RAS precharge 1 2 2 COL #1 ;;;;;;;;; ;;;;;;;;; BCLK A[11:0] ROW #1 ROW #2 tRAS #RAS #CAS #RD ;;;;; ;;;;; D[15:0](RD) ;; ;; RD data #WE D[15:0](WR) ;;; ;;; WR data DRAM: 70ns, CPU: 25/20MHz, page-mode read/write cycle RAS cycle CAS cycle CAS cycle RAS precharge 1 2 2 2 COL #2 ;;;;;;;;; ;;;;;;;;; BCLK A[11:0] ROW #1 COL #1 tRAS #RAS #CAS #RD ;;;;; ;
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS A.2 DRAM (60ns) DRAM interface setup examples – 60ns Operating frequency RAS precharge cycle RAS cycle CAS cycle 20MHz 25MHz 33MHz 1 2 2 1 1 2 2 2 2 Refresh RAS pulse Refresh RPC delay width 2 2 3 1 1 1 DRAM interface timing – 60ns DRAM interface Parameter Unit: ns 33MHz 25MHz 20MHz Symbol Min. Max.
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS DRAM: 60ns, CPU: 33MHz, random read/write cycle tRC RAS cycle CAS cycle RAS precharge 2 2 2 ROW #1 COL #1 ;;;;;;;;; ;;;;;;;;; BCLK A[11:0] tRAD tRAH tASC tRAS tASR ROW #2 tRP #RAS tRCD tCAS #CAS #RD tRAC tOAC tAA tCAC tOFF ;;;;; t;;;;; D[15:0](RD) RD data ;;;; ;;;; WP #WE tDS D[15:0](WR) tDH WR data ;;; ;;; DRAM: 60ns, CPU: 33MHz, page-mode read/write cycle tPC RAS cycle CAS cycle CAS cycle RAS precharge 2 2 2 2
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS DRAM: 60ns, CPU: 25MHz, random read/write cycle RAS cycle CAS cycle RAS precharge 1 2 2 COL #1 ;;;;;;;;; ;;;;;;;;; BCLK A[11:0] ROW #1 ROW #2 tRAS #RAS #CAS #RD ;;;;; ;;;;; D[15:0](RD) ;; ;; RD data #WE D[15:0](WR) ;;; ;;; WR data DRAM: 60ns, CPU: 25MHz, page-mode read/write cycle RAS cycle CAS cycle CAS cycle RAS precharge 1 2 2 2 COL #2 ;;;;;;;;; ;;;;;;;;; BCLK A[11:0] ROW #1 COL #1 tRAS #RAS #CAS #RD ;;;;; ;;;;;
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS DRAM: 60ns, CPU: 20MHz, random read/write cycle RAS cycle CAS cycle RAS precharge 1 2 1 COL #1 ;;;;; ;;;;; BCLK A[11:0] ROW #1 ROW #2 tRAS #RAS #CAS #RD ;;;;; ;;;;; D[15:0](RD) ;; ;; RD data #WE D[15:0](WR) ;;; ;;; WR data DRAM: 60ns, CPU: 20MHz, page-mode read/write cycle RAS cycle CAS cycle CAS cycle RAS precharge 1 2 2 1 BCLK A[11:0] ROW #1 COL #1 ;;;;;; ;;;;;; COL #2 tRAS #RAS #CAS #RD ;;;;; ;;;;; D[15:0](RD) R
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS A.3 ROM and Burst ROM Burst ROM and mask ROM interface setup examples Operating Normal read cycle Burst read cycle Output disable frequency Wait cycle Read cycle Wait cycle Read cycle delay cycle 20MHz 25MHz 33MHz 2 3 4 3 4 5 1 1 2 2 2 3 1.5 1.5 1.
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS ROM: 100ns, CPU: 25MHz, normal read BCLK ;;;;; ;;;;; A[23:0] #CE9, 10 #RD ;;;;;;;;;;; ;;;;;;;;;;; D[15:0] ;;;; ;;;; RD data ROM: 100ns, CPU: 25MHz, burst read BCLK Normal read cycle Burst read cycle ;;; ;;; A[23:0] #CE9, 10 #RD ;;;;;; ;;;;;; ;;; ;;; ;;; ;;; ;;; ;;; RD data D[15:0] RD data RD data ;;; ;;; RD data ROM: 100ns, CPU: 20MHz, normal read BCLK ;;;;; ;;;;; A[23:0] #CE9, 10 #RD D[15:0] ;;;;;;; ;;;;;;; ;;;; ;;;; RD data
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS A.4 SRAM (55ns) SRAM interface setup examples – 55ns Operating Read cycle Output disable Write cycle frequency Wait cycle Read cycle 20MHz 25MHz 33MHz 1 2 2 2 3 3 delay time 2 3 3 1.5 1.5 1.5 SRAM interface timing – 55ns SRAM interface 33MHz Parameter 25MHz 20MHz Symbol Min. Max. Cycle Time Cycle Time Cycle Time t RC t ACC t ACS t OE t OHZ 55 – – – 0 – 55 55 30 30 3 3 3 2.5 1.5 90 90 90 75 45 3 3 3 2.5 1.
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS SRAM: 55ns, CPU: 20MHz, read cycle BCLK ;;;;; ;;;;; A[23:0] #CEx #RD ;;;;; ;;;;; RD data D[15:0] ;;;; ;;;; SRAM: 55ns, CPU: 20MHz, write cycle BCLK ;;;;; ;;;;; A[23:0] #CEx #WP D[15:0] S1C33210 PRODUCT PART WR data EPSON ;;; ;;; A-103
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS A.5 SRAM (70ns) SRAM interface setup examples – 70ns Operating Read cycle Output disable Write cycle frequency Wait cycle Read cycle 20MHz 25MHz 33MHz 2 2 3 3 3 4 delay time 3 3 4 1.5 1.5 1.5 SRAM interface timing – 70ns SRAM interface 33MHz Parameter 25MHz 20MHz Symbol Min. Max. Cycle Time Cycle Time Cycle Time t RC t ACC t ACS t OE t OHZ 70 – – – 0 – 70 70 40 30 4 4 4 3.5 1.5 120 120 120 105 45 3 3 3 2.5 1.
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS SRAM: 70ns, CPU: 25/20MHz, read cycle BCLK ;;;;; ;;;;; A[23:0] #CEx #RD ;;;;;;;;; ;;;;;;;;; RD data D[15:0] ;;;; ;;;; SRAM: 70ns, CPU: 25/20MHz, write cycle BCLK ;;;;; ;;;;; A[23:0] #CEx #WP D[15:0] S1C33210 PRODUCT PART WR data EPSON ;;; ;;; A-105
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS A.6 8255A 8255A interface setup examples Operating Read cycle frequency Wait cycle 20MHz 25MHz 33MHz 9 11 14 Output disable Write cycle Read cycle ∗1 delay time 10 12 15 10 12 15 3.5 3.5 3.5 ∗2 8255A interface timing SRAM interface Parameter 33MHz 25MHz 20MHz Symbol Min. Max. Cycle Time Cycle Time Cycle Time t RC t ACC t ACS t OE t OHZ 300 – – – 10 – 250 250 250 150 15 15 15 14.5 3.5 450 450 450 435 105 12 12 12 11.
APPENDIX B PIN CHARACTERISTICS Appendix B Pin Characteristics Pin No.
APPENDIX B PIN CHARACTERISTICS Pin No.
APPENDIX B Pin No.
APPENDIX B PIN CHARACTERISTICS THIS PAGE IS BLANK.
S1C33210 FUNCTION PART
S1C33210 FUNCTION PART I OUTLINE
I OUTLINE: INTRODUCTION I-1 INTRODUCTION The Function Part gives a detailed description of the various function blocks built into the Seiko Epson original 32-bit microcomputer S1C33210. The S1C33210 employs a RISC type CPU, and has a powerful instruction set capable of compilation into compact code, despite the small CPU core size.
I OUTLINE: INTRODUCTION THIS PAGE IS BLANK.
I OUTLINE: BLOCK DIAGRAM I-2 BLOCK DIAGRAM The S1C33210 consists of five major blocks: C33 Core Block, C33 Peripheral Block, C33 Analog Block, C33 DMA Block and C33 Internal Memory Block. Figure 2.1 shows the configuration of the S1C33 blocks.
I OUTLINE: BLOCK DIAGRAM C33 Core Block The C33 Core Block consists of a functional block C33_CORE including CPU, BCU (Bus Control Unit), ITC (Interrupt Controller), CLG (Clock Generator) and DBG (Debug Unit), an I/O pad block for external interface, and an SBUS (Internal Silicon Integration Bus) for interfacing with on-chip Peripheral Macro Cells. The C33 Core Block employs the S1C33000 32-bit RISC type CPU as the core CPU.
I OUTLINE: LIST OF PINS I-3 LIST OF PINS List of External I/O Pins The following lists the external I/O pins of the C33 Core Block and Peripheral Block. Note that some pins are listed in two or more tables. Table 3.1 List of Pins for External Bus Interface Signals Pin name I/O Pull-up O – A0: #BSL: A[23:1] O – Address bus (A1 to A23) D[15:0] I/O – Data bus (D0 to D15) #CE10EX O – Area 10 chip enable for external memory * When CEFUNC[1:0] = "1x", this pin outputs #CE9+#CE10EX signal.
I OUTLINE: LIST OF PINS I/O Pull-up P30 #WAIT #CE4&5 Pin name I/O – P30: #WAIT: #CE4&5: Function P20 #DRD I/O – P20: #DRD: P21 #DWE #GAAS I/O – P21: #DWE: P31 #BUSGET #GARD I/O – P31: I/O port when CFP31(D1/0x402DC) = "0" and CFEX3(D3/0x402DF) = "0" (default) #BUSGET: Bus status monitor signal output when CFP31(D1/0x402DC) = "1" and CFEX3(D3/0x402DF) = "0" #GARD: Area read signal output for GA when CFEX3(D3/0x402DF) = "1" EA10MD1 I I/O port when CFP20(D0/0x402D8) = "0" (default) DRAM
I OUTLINE: LIST OF PINS Table 3.3 List of Pins for Internal Peripheral Circuits Pin name I/O Pull-up Function K52 #ADTRG I Pull-up K52: #ADTRG: K60 AD0 I – K60: AD0: Input port when CFK60(D0/0x402C3) = "0" (default) A/D converter Ch. 0 input when CFK60(D0/0x402C3) = "1" K61 AD1 I – K61: AD1: Input port when CFK61(D1/0x402C3) = "0" (default) A/D converter Ch. 1 input when CFK61(D1/0x402C3) = "1" K62 AD2 I – K62: AD2: Input port when CFK62(D2/0x402C3) = "0" (default) A/D converter Ch.
I OUTLINE: LIST OF PINS Pin name I/O Pull-up P16 EXCL5 #DMAEND1 I/O – P16: EXCL5: Function P20 #DRD I/O – P20: #DRD: P21 #DWE #GAAS I/O – P21: #DWE: P22 TM0 I/O – P22: TM0: I/O port when CFP22(D2/0x402D8) = "0" (default) 16-bit timer 0 output when CFP22(D2/0x402D8) = "1" P23 TM1 I/O – P23: TM1: I/O port when CFP23(D3/0x402D8) = "0" (default) 16-bit timer 1 output when CFP23(D3/0x402D8) = "1" P24 TM2 #SRDY2 I/O – P24: TM2: #SRDY2: I/O port when CFP24(D4/0x402D8) = "0" (default)
I OUTLINE: LIST OF PINS Table 3.
I OUTLINE: LIST OF PINS THIS PAGE IS BLANK.
S1C33210 FUNCTION PART II CORE BLOCK
II CORE BLOCK: INTRODUCTION II-1 INTRODUCTION The core block consists of a functional block C33_CORE including CPU, BCU (Bus Control Unit), ITC (Interrupt Controller), CLG (Clock Generator) and DBG (Debug Unit), an I/O pad block for external interface, and an SBUS (Internal Silicon Integration Bus) for interfacing with on-chip Peripheral Macro Cells.
II CORE BLOCK: INTRODUCTION THIS PAGE IS BLANK.
II CORE BLOCK: CPU AND OPERATING MODE II-2 CPU AND OPERATING MODE CPU The C33 Core Block employs the S1C33000 32-bit RISC type CPU as the core CPU. Since it has a built-in multiplier, all instructions (105 instructions) in the S1C33000 instruction set including the MAC (multiplication and accumulation) instruction and the multiplication/division instructions are available. All the internal registers of the S1C33000 can be used. The CPU registers and CPU address bus can handle 28-bit addresses.
II CORE BLOCK: CPU AND OPERATING MODE Standby Mode The CPU supports three standby modes: two HALT modes and a SLEEP mode. By setting the CPU in the standby mode, power consumption can greatly be reduced. HALT Mode When the CPU executes the halt instruction, it suspends the program execution and enters the HALT mode. The CPU supports two types of HALT modes (basic HALT mode and HALT2 mode) and either can be selected using the HLT2OP (D3) / Clock option register (0x40190).
II CORE BLOCK: CPU AND OPERATING MODE Notes on Standby Mode Interrupts The standby mode can be canceled by an interrupt. Therefore, it is necessary to enable the interrupt to be used for canceling the standby mode before setting the CPU in the standby mode. It is also necessary to set the IE (interrupt enable) and IL (interrupt level) bits in the PSR to a condition that can accept the interrupt. Otherwise, the standby mode cannot be canceled even when an interrupt occurs.
II CORE BLOCK: CPU AND OPERATING MODE Trap Table Table 2.1 shows the trap table in the C33 Core. Refer to the "S1C33000 Core CPU Manual" for details of exceptions and Section II-5 in this manual, "ITC (Interrupt Controller)", for interrupts. Serial interface Ch.2 and Ch.3 interrupts share the trap table for port input interrupts and 16-bit timer interrupts. Refer to Section III-8, "Serial Interface", for details of the settings. Table 2.1 Trap Table HEX Vector number No.
II CORE BLOCK: CPU AND OPERATING MODE HEX Vector number No. (Hex address) Exception/interrupt name Serial interface Ch.0 Exception/interrupt factor IDMA Ch. Priority 38 56(Base+E0) Receive error – High 39 57(Base+E4) Receive buffer full 23 ↑ 3A 58(Base+E8) Transmit buffer empty 24 59 reserved – – 3C 60(Base+F0) Serial interface Ch.
II CORE BLOCK: CPU AND OPERATING MODE THIS PAGE IS BLANK.
II CORE BLOCK: INITIAL RESET II-3 INITIAL RESET Pins for Initial Reset Table 3.1 shows the pins used for initial reset. Table 3.1 Pins for Initial Reset Pin name I/O #RESET I #MNI I Function Initial reset input pin (Low active) Low: Resets the CPU. NMI request input pin This pin is also used for selecting a reset method. High: Cold start Low: Hot start The chip is reset when the #RESET pin goes low and starts operating at the rising edge of the reset signal.
II CORE BLOCK: INITIAL RESET Power-on Reset Be sure to reset (cold start) the chip after turning on the power to start operating. Since the #RESET pin is directly connected to an input gate, a power-on reset circuit should be configured outside the chip. An initial reset (#RESET = low) turns the high-speed (OSC3) oscillation circuit on. The CPU starts operating with the OSC3 clock at the rising edge of the reset signal. The high-speed (OSC3) oscillation circuit takes time (10 ms max.
II CORE BLOCK: INITIAL RESET Boot Address When the core CPU is initially reset, it reads the reset vector (program start address) from the boot address (0x0C00000) and loads the vector to the PC (program counter). Then the CPU starts executing the program from the address when the #RESET pin goes high. The trap table in which trap vectors for interrupts and other trap factors are written also begins from the boot address by the default setting.
II CORE BLOCK: INITIAL RESET THIS PAGE IS BLANK.
II CORE BLOCK: BCU (Bus Control Unit) II-4 BCU (Bus Control Unit) The BCU (Bus Control Unit) provides an interface for external devices and on-chip user logic block. The types and sizes of memory and peripheral I/O devices can be set for each area of the memory map and can be controlled directly by the BCU. This unit also supports a direct interface for DRAM and burst ROM. This chapter describes how to control the external and internal system interface, and how it operates.
II CORE BLOCK: BCU (Bus Control Unit) User interface signals Table 4.2 List of User Interface Signals Signal name I/O Function Internal_addr0 O • Address bus (a0) when SBUSST(D3/0x4812E) = "0" (default) • Bus strobe (low byte) signal (#BSL) when SBUSST(D3/0x4812E) = "1" Internal_addr[23:1] Internal_dout[15:0] O Address bus (a1 to a23) O Output data bus (dout0 to dout15) This data bus is used when the CPU writes data to the on-chip user logic.
II CORE BLOCK: BCU (Bus Control Unit) Combination of System Bus Control Signals The bus control signal pins that have two or more functions have their functionality determined when an interface method is selected by a program. The BCU contains an ordinary external system interface (two interface method are supported) and a DRAM interface. Table 4.
II CORE BLOCK: BCU (Bus Control Unit) Memory Area Memory Map Figure 4.1 shows the memory map supported by the BCU.
II CORE BLOCK: BCU (Bus Control Unit) External Memory Map and Chip Enable The BCU has a 24-bit external address bus (A[23:0]) and a 16-bit external data bus (D[15:0]), allowing an address space of up to 16 MB to be accessed with one chip enable signal. By default, the address space is divided into 11 areas (areas 0 to 10) for management purposes. Of these, areas 4 to 10 are open to an external system, each provided with an independent chip-enable pin (#CE[10:4]).
II CORE BLOCK: BCU (Bus Control Unit) Area Area 17+18 (#CE17+18) SRAM type 8 or 16 bits Areas 15–16 (#CE15+16) SRAM type 8 or 16 bits Area 14 (#CE14/#RAS3) SRAM type DRAM type 8 or 16 bits Area 13 (#CE13/#RAS2) SRAM type DRAM type 8 or 16 bits Areas 11–12 (#CE11+12) SRAM type 8 or 16 bits Areas 9–10 (#CE9+10EX) SRAM type Burst ROM type 8 or 16 bits Areas 7–8 (#CE7+8) SRAM type 8 or 16 bits Address 0xFFFFFFF 0xD000000 0xCFFFFFF 0xC000000 0xBFFFFFF 0x9000000 0x8FFFFFF 0x8000000 0x7FFFFFF 0x7000000 0x6FFF
II CORE BLOCK: BCU (Bus Control Unit) Using Internal Memory on External Memory Area The BCU allows using of an internal memory in the external memory areas. The AxxIO bit in the access control register (0x48132) is used to select either internal access or external access. When "1" is written, the internal device will be accessed and when "0" is written, the external device is accessed (external access by default).
II CORE BLOCK: BCU (Bus Control Unit) Area 10 Area 10 is an external memory area that includes the boot address (0xC00000). Area 10 boot mode The boot mode can be configured using the external pins EA10MD[1:0]. The pins EA10MD[1:0] specify the boot mode. These inputs must both be at High level because this device supports only one boot mode, from external ROM. Table 4.
II CORE BLOCK: BCU (Bus Control Unit) Setting External Bus Conditions The type, size, and wait conditions of a device connected to the external bus can be individually set for each area using the control register (0x48120 to 0x48130). The following explains the available setup conditions individually for each area. For details on how to set the DRAM interface conditions, refer to "DRAM Direct Interface". The control register used to set bus conditions is initialized at cold start.
II CORE BLOCK: BCU (Bus Control Unit) Setting SRAM Timing Conditions The areas set for the SRAM allow wait cycles and output disable delay time to be set. Number of wait cycles: 0 to 7 (incremented in units of one cycle) Output disable delay time: 0.5, 1.5, 2.5, 3.5 cycles This selection can be made once every two areas except for area 6. Table 4.
II CORE BLOCK: BCU (Bus Control Unit) Output disable delay time In cases when a device having a long output disable time is connected, if a read cycle for that device is followed by the next access, contention for the data bus may occur. (Due to the fact the read device's data bus is not placed in the high-impedance state.) The output disable delay time is provided to prevent such data bus contention.
II CORE BLOCK: BCU (Bus Control Unit) Bus Operation Data Arrangement in Memory The S1C33 Family of devices handle data in bytes (8 bits), half-words (16 bits), and words (32 bits). When accessing data in memory, it is necessary to specify a boundary address that conforms to the data size involved. Specification of an invalid address causes an address error exception. For instructions (e.g.
II CORE BLOCK: BCU (Bus Control Unit) These bus operations are shown in the figure below, taking the example of the A0 method. With the BSL method, the following adjustments should be made when reading the figure. (1) For data reads, the operation is as shown in the figure below. (2) For little-endian data writes, read A0 as #BSC, and #WRH as #BSH. (3) For big-endian data writes, read A0 as #BSL, and #WRL as #BSH. For information on memory connection, see Figure 4.18.
II CORE BLOCK: BCU (Bus Control Unit) Little-endian 31 Destination (general-purpose register) Sign or Zero extension Byte 1 Byte 0 1 15 Bus operation 0 0 No. A1 A0 #WRH #WRL 15 Data bus 1 Byte 1 Byte 0 ∗ 0 1 1 0 A[1:0]=∗0 Source (16-bit device) Big-endian 31 Destination (general-purpose register) Sign or Zero extension Byte 1 Byte 0 1 15 Bus operation 0 0 No. A1 A0 #WRH #WRL 15 Data bus Byte 1 Byte 0 1 ∗ 0 1 1 0 A[1:0]=∗0 Source (16-bit device) Figure 4.
II CORE BLOCK: BCU (Bus Control Unit) Little-endian 31 8 Destination (general-purpose register) Byte 3 Byte 2 Byte 1 Byte 0 4 0 8 A[1:0]=11 3 0 8 A[1:0]=10 2 1 0 8 A[1:0]=01 Bus operation 0 0 A[1:0]=00 Source (8-bit device) No.
II CORE BLOCK: BCU (Bus Control Unit) Little-endian Destination (general-purpose register) Sign or Zero extension Byte 0 31 1 8 Bus operation 0 0 No. A1 A0 #WRH #WRL 15 Data bus 1 Ignored Byte 0 ∗ ∗ X 1 0 A[1:0]=∗∗ (X: Not connected/Unused) Source (8-bit device) Big-endian Destination (general-purpose register) Sign or Zero extension Byte 0 31 1 8 0 Bus operation 0 No. A1 A0 #WRH #WRL 15 Data bus 0 Byte 0 Ignored 1 ∗ ∗ 1 1 A[1:0]=∗∗ Source (8-bit device) Figure 4.
II CORE BLOCK: BCU (Bus Control Unit) Since the bus clock is generated from the CPU system clock (CPU_CLK), the following settings affect the bus clock: 1. Selection of an oscillation circuit (OSC3 or OSC1) 2. PLL configuration (OSC3_CLK ×1, ×2 or ×4) 3. CPU clock division ratio for power saving (1/8, 1/4, 1/2, or 1/1 of OSC3_CLK or PLL_CLK) Items 2 and 3 apply when the high-speed (OSC3) oscillation circuit is selected as the CPU clock source.
II CORE BLOCK: BCU (Bus Control Unit) Bus Cycles in External System Interface The following shows a sample SRAM connection the basic bus cycles. S1C33 SRAM S1C33 SRAM S1C33 SRAM A[9:1] D[15:0] A[8:0] I/O[15:0] A[9:1] D[15:0] A[8:0] I/O[15:0] A[9:1] D[15:0] A[8:0] I/O[15:0] #RD #WRH #WRL #CE #RD #WRH #WRL #CE A0 #WRH #WRL #CE #RD #LB #UB #WE #OS #OE A0 #WRH #WRL #CE #RD #LB #UB #WE #OS #OE (1) A0 system (little endian/big endian) (2) #BSL system (little endian) Figure 4.
II CORE BLOCK: BCU (Bus Control Unit) The above example shows a read cycle when a wait mode is inserted via the #WAIT signal. A wait mode consisting of 0 to 7 cycles can also be inserted using the wait control bits. The settings of these bits can also be used in combination with the #WAIT signal. In this case as well, the #WAIT signal is sampled at the falling edge of the transition of BCLK.
II CORE BLOCK: BCU (Bus Control Unit) SRAM Write Cycles Basic write cycle with no wait mode C1 C2 BCLK ;;; ;;; addr A[23:0] #CExx data D[15:0] #WRH/#WRL #WAIT #WR #BSL/#BSH Figure 4.22 C1 Half-word Write Cycle with No Wait C2 C3 C4 BCLK ;;; ;;; addr A[23:0] #CExx #WRH #WRL D[15:8] Undefined Valid D[7:0] Valid Undefined Figure 4.
II CORE BLOCK: BCU (Bus Control Unit) Write cycle with wait mode Example: When the BCU has no internal wait mode, and 1 wait cycle is inserted via the #WAIT pin C1 CW C2 BCLK ;;; ;;; addr A[23:0] #CExx data D[15:0] #WRH/#WRL #WAIT #WR #BSL/#BSH Figure 4.
II CORE BLOCK: BCU (Bus Control Unit) Burst ROM Read Cycles Burst read cycle Example: When 4-consecutive-burst and 2-wait cycles are set during the first access BCLK addr[23:2] A[23:2] A[1:0] #CE10(9) D[15:0] #RD "00" "01" "10" "11" ;;; ;;; ;;; ;;; ;;;;;;;;;;;;;; IR0 ;;;; IR1 ;;;; IR2 ;;;; IR3 ;;;;;;;;;;;;;; ;;;; ;;;; ;;;; Figure 4.
II CORE BLOCK: BCU (Bus Control Unit) DRAM Direct Interface Outline of DRAM Interface The BCU incorporates a DRAM direct interface that allows DRAM to be connected directly to areas 8 and 7 or areas 14 and 13. This interface supports the 2CAS method, so that column addresses can be set at between 8 and 11 bits. In addition, this interface supports a fast-page or an EDO-page mode (EDO DRAM directly connectable to areas) as well as random cycles.
II CORE BLOCK: BCU (Bus Control Unit) DRAM Setting Conditions The DRAM interface allows the following conditions to be selected. Although DRAM can be used in areas 8 and 7 or areas 14 and 13, these condition are applied to all four areas and cannot be set individually for each area. Table 4.
II CORE BLOCK: BCU (Bus Control Unit) Column address size When accessing DRAM, addresses are divided into a row address and a column address as they are output. Choose the size of this column address using RCA, as shown below. Table 4.16 Column Address Size RCA1 RCA0 Column address size 1 1 0 0 1 0 1 0 11 10 9 8 The initial default size is 8 bits. Choose the desired size according to the address input pins of the DRAM to be used.
II CORE BLOCK: BCU (Bus Control Unit) Refresh RPC delay Use RPC0 to set the RPC delay value of a refresh cycle (a delay time from the immediately preceding precharge to the fall of #CAS). RPC0 = "1": 2 cycles RPC0 = "0": 1 cycle Refresh RAS pulse width Use RRA to set the #RAS pulse width of a CAS-before-RAS refresh cycle. Table 4.17 Refresh RAS Pulse Width RRA1 RRA0 1 1 0 0 1 0 1 0 Pulse width 5 4 3 2 cycles cycles cycles cycles The initial default value is 2 cycles.
II CORE BLOCK: BCU (Bus Control Unit) DRAM Read/Write Cycles The following shows the basic bus cycles of DRAM. The DRAM interface does not accept wait cycles inserted via the #WAIT pin. DRAM random read cycle Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle RAS cycle Precharge cycle CAS cycle BCLK A[11:0] ROW ;;;;;;; ;;;;;;; COL #RASx #HCAS/ #LCAS #RD D[15:0] ;;;;;;;;;;;;; ;;;;;;;;;;;;; Figure 4.
II CORE BLOCK: BCU (Bus Control Unit) DRAM random write cycle Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle RAS cycle CAS cycle BCLK ROW A[11:0] COL #RASx Precharge cycle ;;;;;;; ;;;;;;; #HCAS/ #LCAS #WE write data D[15:0] Figure 4.
II CORE BLOCK: BCU (Bus Control Unit) Operation in successive RAS mode Example: RAS: 2 cycles; CAS: 1 cycle; Precharge: 2 cycles (1) RAS cycle CAS cycles in page mode (2) (3) Deassert cycle Assert cycle (4) CAS cycles in page mode Precharge cycle RAS cycle CAS cycles BCLK A[11:0] #RASx #HCAS/ #LCAS #DRD #DWE Accsess to other device than DRAM Figure 4.
II CORE BLOCK: BCU (Bus Control Unit) DRAM Refresh Cycles The DRAM interface supports a CAS-before-RAS refresh cycle and a self-refresh cycle. CAS-before-RAS refresh cycle Before performing a CAS-before-RAS refresh, set RPC2 to "1" while RPC1 = "0" in order to enable the DRAM refresh function. Once this is done, the BCU executes a CAS-before-RAS refresh by using the underflow signal that is output by the 8-bit programmable timer 0 as a trigger.
II CORE BLOCK: BCU (Bus Control Unit) Normally, DRAM specifications require that the contents of all row addresses be refreshed within a certain time before and after a self-refresh. To meet this requirement, make sure a CAS-before-RAS refresh is executed by a program. In this case, set the 8-bit programmable timer 0 so that the contents of all row addresses are refreshed within a predetermined time.
II CORE BLOCK: BCU (Bus Control Unit) DRAM refresh when bus ownership control is released In systems where DRAM is connected directly, a refresh request could arise while control of the bus ownership is released from the CPU. In such a case, take one of the corrective measures described below. • Monitoring the output signal of the 8-bit programmable timer 0 The underflow signal (DRAM refresh request) of the 8-bit programmable timer 0 can be output from the P10 I/O port pin.
II CORE BLOCK: BCU (Bus Control Unit) I/O Memory of BCU Table 4.21 shows the control bits of the BCU. These I/O memories are mapped into the area (0x48000 and following addresses) used for the internal 16-bit peripheral circuits. However, these I/O memories can be accessed in bytes or words, as well as in half-words.
II CORE BLOCK: BCU (Bus Control Unit) Register name Address Bit Areas 12–11 0048124 set-up register (HW) DF–7 D6 D5 D4 – A12SZ A12DF1 A12DF0 D3 D2 D1 D0 – A12WT2 A12WT1 A12WT0 Areas 10–9 0048126 set-up register (HW) Areas 8–7 0048128 set-up register (HW) B-II-4-34 Name DF-B – DA A10BW1 D9 A10BW0 Function Setting Init. R/W Remarks reserved – Areas 12–11 device size selection 1 8 bits 0 16 bits Areas 12–11 A18DF[1:0] Number of cycles 1 1 3.5 output disable delay time 1 0 2.5 0 1 1.5 0 0 0.
II CORE BLOCK: BCU (Bus Control Unit) Register name Address Bit Name Areas 6–4 004812A DF–E – set-up register (HW) DD A6DF1 DC A6DF0 Bus control register 004812E (HW) Function reserved Area 6 output disable delay time DB DA D9 D8 – A6WT2 A6WT1 A6WT0 reserved Area 6 wait control D7 D6 D5 D4 – A5SZ A5DF1 A5DF0 reserved Areas 5–4 device size selection Areas 5–4 output disable delay time D3 D2 D1 D0 – A5WT2 A5WT1 A5WT0 reserved Areas 5–4 wait control DF DE DD DC DB DA RBCLK – RBST8 REDO RCA1 R
II CORE BLOCK: BCU (Bus Control Unit) Register name Address Bit Name Function DRAM timing 0048130 DF–C – reserved set-up register (HW) DB – reserved DA CEFUNC1 #CE pin function selection D9 CEFUNC0 Setting – – CFFUNC[1:0] #CE output 1 x #CE7/8..#CE17/18 #CE6..#CE17 0 1 #CE4..#CE10 0 0 1 Successive 0 Normal RPRC[1:0] Number of cycles 1 1 4 1 0 3 0 1 2 0 0 1 – CASC[1:0] Number of cycles 1 1 4 1 0 3 0 1 2 0 0 1 – RASC[1:0] Number of cycles 1 1 4 1 0 3 0 1 2 0 0 1 Init.
II CORE BLOCK: BCU (Bus Control Unit) A18SZ:Areas 18–17 device size selection (DE) / Areas 18–15 set-up register (0x48120) A16SZ:Areas 16–15 device size selection (D6) / Areas 18–15 set-up register (0x48120) A14SZ:Areas 14–13 device size selection (D6) / Areas 14–13 set-up register (0x48122) A12SZ:Areas 12–11 device size selection (D6) / Areas 12–11 set-up register (0x48124) A10SZ:Areas 10–9 device size selection (D6) / Areas 10–9 set-up register (0x48126) A8SZ: Areas 8–7 device size selection (D6) / Areas
II CORE BLOCK: BCU (Bus Control Unit) At cold start, these bits are set to "111" (7 cycles). At hot start, the bits retain their status before being initialized. A14DRA: Area A13DRA: Area A8DRA: Area A7DRA: Area 14 DRAM selection (D8) / Areas 14–13 set-up register (0x48122) 13 DRAM selection (D7) / Areas 14–13 set-up register (0x48122) 8 DRAM selection (D8) / Areas 8–7 set-up register (0x48128) 7 DRAM selection (D7) / Areas 8–7 set-up register (0x48128) Select the DRAM direct interface.
II CORE BLOCK: BCU (Bus Control Unit) A10DRA: Area 10 burst ROM selection (D8) / Areas 10–9 set-up register (0x48126) A9DRA: Area 9 burst ROM selection (D7) / Areas 10–9 set-up register (0x48126) Set areas 10 and 9 for use of burst ROM. Write "1": Burst ROM is used Write "0": Burst ROM is not used Read: Valid When using burst ROM, write "1" to the control bit. The ordinary SRAM interface is selected by writing "0" to the bit. Area 9 can only be used when the CEFUNC = "00".
II CORE BLOCK: BCU (Bus Control Unit) RCA1–RCA0: Column address size selection (D[B:A]) / Bus control register (0x4812E) Select the column address size of DRAM. Table 4.23 Column Address Size RCA1 RCA0 Column address size 1 1 0 0 1 0 1 0 11 10 9 8 The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. RCA can be read to obtain its set value. At cold start, RCA is set to "0" (8 bits). At hot start, RCA retain its status before being initialized.
II CORE BLOCK: BCU (Bus Control Unit) RRA1–RRA0: Refresh RAS pulse width selection (D[6:5]) / Bus control register (0x4812E) Select the RAS pulse width of a CAS-before-RAS refresh. Table 4.24 Refresh RAS Pulse Width RRA1 RRA0 1 1 0 0 1 0 1 0 Pulse width 5 4 3 2 cycles cycles cycles cycles The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. The RRA can be read to obtain their set value. At cold start, RRA is set to "0" (2 cycles).
II CORE BLOCK: BCU (Bus Control Unit) SWAITE: #WAIT enable (D0) / Bus control register (0x4812E) Enable or disable wait cycle control via the #WAIT pin. Write "1": Enabled Write "0": Disabled Read: Valid A wait request from an SRAM device is made acceptable by writing "1" to SWAITE. The wait request signal input from the #WAIT pin is sampled at each falling edge of the bus clock when executing an SRAM read/write cycle.
II CORE BLOCK: BCU (Bus Control Unit) CRAS: Successive RAS mode (D8) / DRAM timing set-up register (0x48130) Set the successive RAS mode. Write "1": Successive RAS mode Write "0": Normal mode Read: Valid In systems using DRAM, the successive RAS mode is entered by writing "1" to CRAS. In this mode, read/write operations can be performed in page mode even when DRAM accesses do not occur back-to-back.
II CORE BLOCK: BCU (Bus Control Unit) A18IO: Areas 18–17 internal/external access selection (DF) / Access control register (0x48132) A16IO: Areas 16–15 internal/external access selection (DE) / Access control register (0x48132) A14IO: Areas 14–13 internal/external access selection (DD) / Access control register (0x48132) A12IO: Areas 12–11 internal/external access selection (DC) / Access control register (0x48132) A8IO: Areas 8–7 internal/external access selection (DA) / Access control register (0x48132) A
II CORE BLOCK: BCU (Bus Control Unit) A18RD: A16RD: A14RD: A12RD: A8RD: A6RD: A5RD: Areas 18–17 read signal (D7) / G/A read signal control register (0x48138) Areas 16–15 read signal (D6) / G/A read signal control register (0x48138) Areas 14–13 read signal (D5) / G/A read signal control register (0x48138) Areas 12–11 read signal (D4) / G/A read signal control register (0x48138) Areas 8–7 read signal (D2) / G/A read signal control register (0x48138) Area 6 read signal (D1) / G/A read signal control register
II CORE BLOCK: BCU (Bus Control Unit) A1X1MD: Area 1 access speed (D3) / BCLK select register (0x4813A) Select a number of access cycles for area 1 in ×2 speed mode. Write "1": 2 cycles Write "0": 4 cycles Read: Valid When ×2 speed mode is set (#X2SPD pin = L) and A1X1MD = "1", area 1 is read/written in 2 cycles of the CPU system clock. When A1X1MD = "0", area 1 is read/written in 4 cycles. When x1 speed mode is set (#X2SPD pin = H), area 1 is always accessed in 2 cycles regardless of the A1X1MD value.
II CORE BLOCK: ITC (Interrupt Controller) II-5 ITC (Interrupt Controller) The C33 Core Block contains an interrupt controller, making it possible to control all interrupts generated by the internal peripheral circuits. This section explains the functions of this interrupt controller centering around the method for controlling maskable interrupts. For details about the various factors and conditions under which interrupts are generated, refer to the description of each peripheral circuit in this manual.
II CORE BLOCK: ITC (Interrupt Controller) Contents of table "Hex No." indicates an interrupt number in hexadecimal value. "Vector number (Address)" indicates the trap table's vector number. The numerals in parentheses show an offset (in bytes) from the starting address (Base) of the trap table. The starting address (Base) of the trap table by default is the boot address, 0xC00000 set at an initial reset. This address can be changed using the TTBR register (0x48134 to 0x48137).
II CORE BLOCK: ITC (Interrupt Controller) Interrupt Factors and Intelligent DMA Several interrupt factors can be set so that they can invoke IDMA startup. When one of these interrupt factors occurs, IDMA is started up before an interrupt request to the CPU. The interrupt request to the CPU is generated after IDMA is completed. (The interrupt request can be disabled by a program.) IDMA is always started up regardless of how the PSR is set. For details, refer to "IDMA Invocation".
II CORE BLOCK: ITC (Interrupt Controller) Trap Table The C33 Core Block allows the base (starting) address of the trap table to be set by the TTBR register.
II CORE BLOCK: ITC (Interrupt Controller) Control of Maskable Interrupts Structure of the Interrupt Controller The interrupt controller is configured as shown in Figure 5.1.
II CORE BLOCK: ITC (Interrupt Controller) The IL is rewritten for only maskable interrupts and not for any other traps (except a reset). The IL is set to level 0 (that is, all interrupts above level 1 are enabled) by an initial reset. Note: As the S1C33000 Core CPU function, the IL allows interrupt levels to be set in the range of 0 to 15. However, since the interrupt priority register in the ITC consists of three bits, interrupt levels in each interrupt system can only be set for up to 8.
II CORE BLOCK: ITC (Interrupt Controller) Interrupt enable register This register controls the output of an interrupt request to the CPU. Only when the interrupt enable bit of this register is set to "1" can an interrupt request to the CPU be enabled by an occurrence of the corresponding interrupt factor. If the bit is set to "0", no interrupt request is made to the CPU even when the corresponding interrupt factor occurs. Interrupt enable bits can be read and written as for other registers.
II CORE BLOCK: ITC (Interrupt Controller) Interrupt Priority Register and Interrupt Levels The interrupt priority register is a 3-bit register provided for each interrupt system. It allows the interrupt levels of a given interrupt system to be set in the range of 0 to 7. The default priorities shown in Table 5.1 can be modified according to system requirements by this setting. The value set in this register is used by the interrupt controller and the CPU as described below.
II CORE BLOCK: ITC (Interrupt Controller) IDMA Invocation The interrupt factors for which IDMA channel numbers are written in Table 5.1 have the function to invoke the intelligent DMA (IDMA). IDMA request register The IDMA request register is used to specify the interrupt factor that invoke an IDMA transfer. If an IDMA request bit is set to "1", the IDMA request will be generated when the corresponding interrupt factor occurs.
II CORE BLOCK: ITC (Interrupt Controller) Interrupt after IDMA transfer To generate an interrupt after completion of IDMA transfer: The interrupt request that has been kept pending can be generated after completion of the DMA transfer. In this case, the interrupt must be enabled by the IDMA control information (DINTEM = "1") in adition to the interrupt controller and the PSR register settings.
II CORE BLOCK: ITC (Interrupt Controller) HSDMA Invocation Some interrupt factors can invoke high-speed DMAs (HSDMA). HSDMA trigger set-up register The DMA block contains four channel of HSDMA circuit. Each channel allows selection of an interrupt factor as the trigger. The HSDMA trigger set-up registers are used for this selection. HSDMA Ch.0: HSD0S[3:0] (D[3:0])/HSDMA Ch.0/1 trigger set-up register (0x40298) HSDMA Ch.1: HSD1S[3:0] (D[7:4])/HSDMA Ch.0/1 trigger set-up register (0x40298) HSDMA Ch.
II CORE BLOCK: ITC (Interrupt Controller) I/O Memory of Interrupt Controller Table 5.3 shows the control bits of the interrupt controller. Table 5.
II CORE BLOCK: ITC (Interrupt Controller) Register name Address Bit 16-bit timer 4/5 0040268 interrupt (B) priority register D7 D6 D5 D4 D3 D2 D1 D0 – P16T52 P16T51 P16T50 – P16T42 P16T41 P16T40 reserved 16-bit timer 5 interrupt level – 0 to 7 reserved 16-bit timer 4 interrupt level – 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 – PSI002 PSI001 PSI000 – P8TM2 P8TM1 P8TM0 reserved Serial interface Ch.
II CORE BLOCK: ITC (Interrupt Controller) Register name Address Bit 16-bit timer 4/5 0040274 interrupt (B) enable register D7 D6 D5–4 D3 D2 D1–0 E16TC5 E16TU5 – E16TC4 E16TU4 – Name 16-bit timer 5 comparison A 16-bit timer 5 comparison B reserved 16-bit timer 4 comparison A 16-bit timer 4 comparison B reserved Function 8-bit timer 0040275 interrupt (B) enable register D7–4 D3 D2 D1 D0 – E8TU3 E8TU2 E8TU1 E8TU0 reserved 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit
II CORE BLOCK: ITC (Interrupt Controller) Register name Address Bit Port input 4–7, 0040287 clock timer, A/D (B) interrupt factor flag register D7–6 D5 D4 D3 D2 D1 D0 Port input 0–3, high-speed DMA Ch. 0/1, 16-bit timer 0 IDMA request register Name Function – FP7 FP6 FP5 FP4 FCTM FADE reserved Port input 7 Port input 6 Port input 5 Port input 4 Clock timer A/D converter Setting – 1 Factor is generated 0 No factor is generated Init. R/W Remarks – X X X X X X – 0 when being read.
II CORE BLOCK: ITC (Interrupt Controller) Register name Address Bit Name High-speed DMA Ch.0/1 trigger set-up register D7 D6 D5 D4 HSD1S3 HSD1S2 HSD1S1 HSD1S0 High-speed DMA Ch.1 trigger set-up D3 D2 D1 D0 HSD0S3 HSD0S2 HSD0S1 HSD0S0 High-speed DMA Ch.0 trigger set-up D7 D6 D5 D4 HSD3S3 HSD3S2 HSD3S1 HSD3S0 High-speed DMA Ch.3 trigger set-up D3 D2 D1 D0 HSD2S3 HSD2S2 HSD2S1 HSD2S0 High-speed DMA Ch.2 trigger set-up High-speed DMA Ch.
II CORE BLOCK: ITC (Interrupt Controller) Register name Address Bit Interrupt factor 00402C5 FP function switching register D7 D6 T8CH5S0 SIO3TS0 8-bit timer 5 underflow SIO Ch.3 transmit buffer empty D5 D4 T8CH4S0 SIO3RS0 8-bit timer 4 underflow SIO Ch.3 receive buffer full D3 SIO2TS0 SIO Ch.2 transmit buffer empty D2 SIO3ES0 SIO Ch.3 receive error D1 SIO2RS0 SIO Ch.2 receive buffer full D0 SIO2ES0 SIO Ch.
II CORE BLOCK: ITC (Interrupt Controller) Register name Address Areas 10–9 0048126 set-up register (HW) Bit Name DF-B – DA A10BW1 D9 A10BW0 Function reserved Areas 10–9 burst ROM burst read cycle wait control D8 D7 D6 D5 D4 A10DRA A9DRA A10SZ A10DF1 A10DF0 Area 10 burst ROM selection Area 9 burst ROM selection Areas 10–9 device size selection Areas 10–9 output disable delay time D3 D2 D1 D0 – A10WT2 A10WT1 A10WT0 reserved Areas 10–9 wait control Setting – A10BW[1:0] Wait cycles 1 1 3 1 0 2 0 1 1
II CORE BLOCK: ITC (Interrupt Controller) Fxxx: Interrupt factor flag Indicate the status of interrupt factors generated.
II CORE BLOCK: ITC (Interrupt Controller) DExxx: IDMA enable register Enable or disable the IDMA request. When using the set-only method (default) Write "1": IDMA enabled Write "0": Not changed Read: Valid When using the read/write method Write "1": IDMA enabled Write "0": IDMA disabled Read: Valid If a bit of this register is set to "1", the IDMA request by the interrupt factor is enabled. If the register bit is set to "0", the IDMA request is disabled.
II CORE BLOCK: ITC (Interrupt Controller) DENONLY: IDMA enable register set method selection (D2) / Flag set/reset method select register (0x4029F) Select the method for setting the IDMA enable registers. Write "1": Set-only method Write "0": Read/write method Read: Valid With the set-only method, IDMA enable bits are set by writing "1". The IDMA enable bits for which "0" has been written can neither be set nor reset. Therefore, this method ensures that only a specific IDMA enable bit is set.
II CORE BLOCK: ITC (Interrupt Controller) SIO2TS0: SIO Ch.2 transmit-buffer empty/FP3 interrupt factor switching (D3) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": SIO Ch.2 transmit-buffer empty Write "0": FP3 input Read: Valid Set to "1" to use the SIO Ch.2 transmit-buffer empty interrupt. Set to "0" to use the FP3 input interrupt. At power-on, this bit is set to "0". SIO3RS0: SIO Ch.
II CORE BLOCK: ITC (Interrupt Controller) SIO2RS1: SIO Ch.2 receive-buffer full/TM16 Ch.5 compare B interrupt factor switching (D0) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. Write "1": SIO Ch.2 receive-buffer full Write "0": TM16 Ch.5 compare B Read: Valid Set to "1" to use the SIO Ch.2 receive-buffer full interrupt. Set to "0" to use the TM16 Ch.5 compare B interrupt. At power-on, this bit is set to "0". SIO2TS1: SIO Ch.2 transmit-buffer empty/TM16 Ch.
II CORE BLOCK: ITC (Interrupt Controller) SIO3ES1: SIO Ch.3 receive error/TM16 Ch.3 compare A interrupt factor switching (D5) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. Write "1": SIO Ch.3 receive error Write "0": TM16 Ch.3 compare A Read: Valid Set to "1" to use the SIO Ch.3 receive error interrupt. Set to "0" to use the TM16 Ch.3 compare A interrupt. At power-on, this bit is set to "0". T8CH4S1: 8-bit timer 4 underflow/TM16 Ch.
II CORE BLOCK: ITC (Interrupt Controller) TTBR09–TTBR00: Trap table base address [9:0] (D[9:0]) / TTBR low-order register (0x48134[HW]) TTBR15–TTBR10: Trap table base address [15:10] (D[F:A]) / TTBR low-order register (0x48134[HW]) TTBR2B–TTBR20: Trap table base address [27:16] (D[B:0]) / TTBR high-order register (0x48136[HW]) TTBR33–TTBR30: Trap table base address [31:28] (D[F:C]) / TTBR high-order register (0x48136[HW]) Set the starting address of the trap table.
II CORE BLOCK: ITC (Interrupt Controller) THIS PAGE IS BLANK.
II CORE BLOCK: CLG (Clock Generator) II-6 CLG (Clock Generator) This section describes the method for controlling the system clock. Configuration of Clock Generator The C33 Core Block has a built-in clock generator that consists of a high-speed oscillation circuit (OSC3) and a PLL. The high-speed (OSC3) oscillation circuit generates the main clock for the CPU and internal peripheral circuits (e.g., DMA, serial interface, programmable timer, and A/D converter).
II CORE BLOCK: CLG (Clock Generator) I/O Pins of Clock Generator Table 6.1 lists the I/O pins of the clock generator. Table 6.
II CORE BLOCK: CLG (Clock Generator) PLL The PLL inputs the OSC3 clock and multiply its frequency. The multiply mode should be set using the PLLS[1:0] pins according to the OSC3 clock frequency. Table 6.2 Setting the PLLS[1:0] Pins PLLS1 PLLS0 Mode fin (OSC3 clock) fout 1 1 x2 10 to 25 MHz 20 to 50 MHz 0 1 x4 0 0 PLL Not used 10 to 12.5 MHz 20 to 50 MHz – Not used Figure 6.3 shows a basic external connection diagram for the PLL pins. VDD PLLS1 PLLS0 100 pF PLL 4.
II CORE BLOCK: CLG (Clock Generator) Setting and Switching Over the CPU Operating Clock Setting the CPU operating clock frequency When operating the CPU with the high-speed (OSC3) clock, the operating frequency can be switched over in four steps. Use CLKDT[1:0] (D[7:6]) / Power control register (0x40180) for this switchover. Table 6.
II CORE BLOCK: CLG (Clock Generator) Power-Control Register Protection Flag The power-control register at address 0x40180, which is used to control the oscillation circuits and the CPU operating clock, is normally disabled against writing in order to prevent it from malfunctioning due to unnecessary writing. To enable this register for writing, the power-control register protection flag CLGP[7:0] (D[7:0]) / Power-control protection register (0x4019E) must be set to "0b10010110".
II CORE BLOCK: CLG (Clock Generator) I/O Memory of Clock Generator Table 6.4 lists the control bits of clock generator. Table 6.
II CORE BLOCK: CLG (Clock Generator) CLKCHG: CPU operating clock switch (D2) / Power control register (0x40180) Selects the CPU operating clock. Write "1": OSC3 clock Write "0": OSC1 clock Read: Valid The OSC3 clock is selected as the CPU operating clock by writing "1" to CLKCHG, and OSC1 is selected by writing "0". The operating clock can be switched over in this way only when both the high-speed (OSC3) and lowspeed (OSC1) oscillation circuits are on.
II CORE BLOCK: CLG (Clock Generator) The following shows the operating status in HALT mode (basic mode and HALT2 mode) and SLEEP mode. Table 6.6 Operating Status in Standby Mode Standby mode HALT mode Basic mode Operating status • • • • • • HALT2 mode • • • • • • SLEEP mode • • • • • The CPU clock is stopped. (CPU stop status) BCU clock is supplied. (BCU run status) DMA clock is not stopped. (DMA run status) Clocks for the peripheral circuits maintain the status before entering HALT mode.
II CORE BLOCK: CLG (Clock Generator) Programming Notes (1) Immediately after the high-speed (OSC3) oscillation circuit is turned on, a certain period of time is required for oscillation to stabilize (for a 3.3-V crystal resonator, this time is 10 ms max.). To prevent the device from operating erratically, do not use the clock until its oscillation has stabilized.
II CORE BLOCK: CLG (Clock Generator) THIS PAGE IS BLANK.
II CORE BLOCK: DBG (Debug Unit) II-7 DBG (Debug Unit) Debug Circuit The C33 Core Block has a built-in debug circuit. This functional block is provided to simply realize an advanced software development environment. Note: The debug circuit does not work during normal operation. To construct a software development environment using the debug circuit, the S5U1C33000H (In-Circuit Debugger for S1C33 Family) is separately required.
II CORE BLOCK: DBG (Debug Unit) THIS PAGE IS BLANK.
S1C33210 FUNCTION PART III PERIPHERAL BLOCK
III PERIPHERAL BLOCK: INTRODUCTION III-1 INTRODUCTION The C33 peripheral block consists of a prescaler, six 8-bit programmable timer channels, six 16-bit programmable timer channels including watchdog timer and event counter functions, four serial interface channels, input and I/O ports, a low-speed (OSC1) oscillation circuit, and a clock timer, mobile access interfaces (one PHS, PDC, and HDLC channel each).
III PERIPHERAL BLOCK: INTRODUCTION THIS PAGE IS BLANK.
III PERIPHERAL BLOCK: PRESCALER III-2 PRESCALER Configuration of Prescaler The prescaler divides the source clock (OSC3/PLL output clock or OSC1 clock) to generate the clocks for the internal peripheral circuits. The prescaler division ratio can be selected for each peripheral circuit in a program. A clock control circuit to control the clock supply to each peripheral circuit is also included.
III PERIPHERAL BLOCK: PRESCALER Selecting Division Ratio and Output Control for Prescaler The prescaler has registers for selecting the division ratio and clock output control separately for each peripheral circuit described above, allowing each peripheral circuit to be controlled. The prescaler's division ratio can be selected from among eight ratios set for each peripheral circuit through the use of the division ratio selection bits.
III PERIPHERAL BLOCK: PRESCALER I/O Memory of Prescaler Table 2.3 shows the control bits of the prescaler. Table 2.
III PERIPHERAL BLOCK: PRESCALER Register name Address Bit Name Function 16-bit timer 3 clock control register 004014A D7–4 – (B) D3 P16TON3 D2 P16TS32 D1 P16TS31 D0 P16TS30 reserved 16-bit timer 3 clock control 16-bit timer 3 clock division ratio selection 16-bit timer 4 clock control register 004014B D7–4 – (B) D3 P16TON4 D2 P16TS42 D1 P16TS41 D0 P16TS40 reserved 16-bit timer 4 clock control 16-bit timer 4 clock division ratio selection 16-bit timer 5 clock control register 004014C D7–4 – (B) D
III PERIPHERAL BLOCK: PRESCALER Register name Address Bit Name 8-bit timer 2/3 clock control register D7 D6 D5 D4 P8TON3 P8TS32 P8TS31 P8TS30 004014E (B) D3 D2 D1 D0 A/D clock 004014F control register (B) Power control register 0040180 (B) Prescaler clock 0040181 select register (B) Power control 004019E protect register (B) P8TON2 P8TS22 P8TS21 P8TS20 Function 8-bit timer 3 clock control 8-bit timer 3 clock division ratio selection 8-bit timer 2 clock control 8-bit timer 2 clock division ra
III PERIPHERAL BLOCK: PRESCALER CLGP7–CLGP0:Power-control register protection flag ([D[7:0]) / Power control protection register (0x4019E) These bits remove the protection against writing to addresses 0x40180 and 0x40190. Write "0b10010110": Write protection removed Write other than the above: No operation (write-protected) Read: Valid Before writing to address 0x40180 or 0x40190, set CLGP[7:0] to "0b10010110" to remove the protection against writing to that address.
III PERIPHERAL BLOCK: PRESCALER P16TON0: 16-bit timer 0 clock control (D3) / 16-bit timer 0 clock control register (0x40147) P16TON1: 16-bit timer 1 clock control (D3) / 16-bit timer 1 clock control register (0x40148) P16TON2: 16-bit timer 2 clock control (D3) / 16-bit timer 2 clock control register (0x40149) P16TON3: 16-bit timer 3 clock control (D3) / 16-bit timer 3 clock control register (0x4014A) P16TON4: 16-bit timer 4 clock control (D3) / 16-bit timer 4 clock control register (0x4014B) P16TON5: 16-bi
III PERIPHERAL BLOCK: PRESCALER 1)Blocks that use an operating clock generated by the prescaler • 16-bit programmable timers 0 to 5 (watchdog timer) • 8-bit programmable timers 0 to 5 (DRAM refresh, serial interface) • A/D converter 2)Blocks that use the clock supplied to the prescaler (the prescaler source clock) • 16-bit programmable timers 0 to 5 (watchdog timer) • 8-bit programmable timers 0 to 5 (DRAM refresh) • A/D converter • Serial interface • Ports If none of the blocks in groups 1 and 2 above are
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS III-3 8-BIT PROGRAMMABLE TIMERS Configuration of 8-Bit Programmable Timer The Peripheral Block contains six channels of 8-bit programmable timers (timers 0 to 5). Figure 3.1 shows the structure of the 8-bit programmable timer.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS Uses of 8-Bit Programmable Timers The down-counter of the 8-bit programmable timer cyclically outputs an underflow signal according to the preset data that is set in the software. This underflow signal is used to generate an interrupt request to the CPU or to control the internal peripheral circuits. In addition, this signal can be output to external devices.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS 8-bit programmable timer 2 • Clock supply to the Ch.0 serial interface When using the Ch.0 serial interface in the clock-synchronized master mode or the internal clock-based asynchronous mode, the output clock derived from the underflow signal of the 8-bit programmable timer 2 by dividing it by 2 is supplied to the serial interface as its operating clock. This enables the transfer rate of the serial interface to be programmed.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS Control and Operation of 8-Bit Programmable Timer With the 8-bit programmable timer, the following settings must first be made before it starts counting: 1. Setting the output pin (only when necessary) 2. Setting the input clock 3. Setting the preset data (initial counter value) 4. Setting the interrupt/IDMA/HSDMA Setting of an output pin is necessary only when the output clock of the 8-bit programmable timer is supplied to external devices.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS Setting preset data (initial counter value) Each timer has an 8-bit down-counter and a reload data register. The reload data register RLDx is used to set the initial value of the down-counter of each timer.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS When both the timer RUN/STOP control bit (PTRUNx) and the timer preset bit (PSETx) are set to "1" at the same time, the timer starts counting after presetting the reload register value into the counter. PTRUNx PSETx RLDx 0x10 0xA6 0xF3 Input clock PTDx7 PTDx6 PTDx5 PTDx4 PTDx3 PTDx2 PTDx1 PTDx0 Timer initial setup Preset Reload and interrupt Figure 3.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS Control of Clock Output When outputting an underflow signal of the 8-bit programmable timer to external devices, or when supplying a clock generated by the underflow signal to the serial interface, it is necessary to control the clock output of the timer.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS 8-Bit Programmable Timer Interrupts and DMA The 8-bit programmable timer has a function to generate an interrupt based on the underflow state of the timer 0 to 3. The timing at which an interrupt is generated is shown in Figure 3.2 in the preceding section. Control registers of the interrupt controller Table 3.3 shows the interrupt controller's control register provided for each timer. Table 3.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS High-speed DMA The underflow interrupt factor of the timer 0 to 3 can also invoke high-speed DMA (HSDMA). The following shows the HSDMA channel number and trigger set-up bit corresponding to the timer 0 to 3: Table 3.5 HSDMA Trigger Set-up Bits Timer Timer Timer Timer Timer HSDMA channel 0 1 2 3 0 1 2 3 Trigger set-up bits HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 HSD2S[3:0] (D[3:0]) / HSDMA Ch.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS I/O Memory of 8-Bit Programmable Timers Table 3.6 shows the control bits of the 8-bit programmable timers. For details on the I/O memory of the prescaler used to set a clock, refer to "Prescaler". Table 3.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS Register name Address Bit Name Function 8-bit timer 3 004016C D7–3 – control register (B) D2 PTOUT3 D1 PSET3 D0 PTRUN3 reserved 8-bit timer 3 clock output control 8-bit timer 3 preset 8-bit timer 3 Run/Stop control 8-bit timer 3 reload data register 004016D (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD37 RLD36 RLD35 RLD34 RLD33 RLD32 RLD31 RLD30 8-bit timer 3 reload data RLD37 = MSB RLD30 = LSB 8-bit timer 3 counter data register 004016E (B) D7 D6 D5 D4 D3 D2
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS Register name Address Bit 8-bit timer 0040275 interrupt (B) enable register D7–4 D3 D2 D1 D0 – E8TU3 E8TU2 E8TU1 E8TU0 Name reserved 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow Function 8-bit timer 0040285 interrupt factor (B) flag register D7–4 D3 D2 D1 D0 – F8TU3 F8TU2 F8TU1 F8TU0 reserved 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow Setting I
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS CFP13–CFP10: P1[3:0] pin function selection (D[3:0]) / P1 function select register (0x402D4) Selects the pin that is used to output a timer underflow signal to external devices. Write "1": Underflow signal output pin Write "0": I/O port pin Read: Valid Select the pin used to output a timer underflow signal to external devices from among P10 through P13 by writing "1" to the corresponding bit, CFP10 through CFP13.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS PTD07–PTD00: Timer 0 PTD17–PTD10: Timer 1 PTD27–PTD20: Timer 2 PTD37–PTD30: Timer 3 PTD47–PTD40: Timer 4 PTD57–PTD50: Timer 5 counter counter counter counter counter counter data (D[7:0]) / 8-bit timer 0 data (D[7:0]) / 8-bit timer 1 data (D[7:0]) / 8-bit timer 2 data (D[7:0]) / 8-bit timer 3 data (D[7:0]) / 8-bit timer 4 data (D[7:0]) / 8-bit timer 5 counter counter counter counter counter counter data (0x40162) data (0x40166) data (0x4016A) data (0x4016
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS PTOUT0: Timer 0 PTOUT1: Timer 1 PTOUT2: Timer 2 PTOUT3: Timer 3 PTOUT4: Timer 4 PTOUT5: Timer 5 clock output clock output clock output clock output clock output clock output control control control control control control register (D2) / 8-bit timer 0 control register (0x40160) register (D2) / 8-bit timer 1 control register (0x40164) register (D2) / 8-bit timer 2 control register (0x40168) register (D2) / 8-bit timer 3 control register (0x4016C) register (
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS F8TUx is the interrupt factor flag corresponding to each timer. It is set to "1" when the counter underflows. At this time, if the following conditions are met, an interrupt to the CPU is generated: 1. The corresponding interrupt enable register bit is set to "1". 2. No other interrupt request of a higher priority has been generated. 3. The IE bit of the PSR is set to "1" (interrupts enabled). 4.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS DE8TU0: Timer 0 IDMA enable (D2) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register (0x40296) DE8TU1: Timer 1 IDMA enable (D3) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register (0x40296) DE8TU2: Timer 2 IDMA enable (D4) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register (0x40296) DE8TU3: Timer 3 IDMA enable (D5) / 16-bit timer 5, 8-bit timer, serial I/F Ch.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS THIS PAGE IS BLANK.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS III-4 16-BIT PROGRAMMABLE TIMERS Configuration of 16-Bit Programmable Timer The Peripheral Block contains six systems of 16-bit programmable timers (timers 0 to 5). They also have an event counter function using an I/O port pin. Note: On the following pages, each timer is identified as timer x (x = 0 to 5). The functions and control register structures of 16-bit programmable timers 0 to 5 are the same.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS I/O Pins of 16-Bit Programmable Timers Table 4.1 shows the input/output pins used for the 16-bit programmable timers. Table 4.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Uses of 16-Bit Programmable Timers The up-counters of the 16-bit programmable timer cyclically output a comparison-match signal in accordance with the comparison data that are set in the software. This signal is used to generate an interrupt request to the CPU or control the internal peripheral circuits. A clock generated from the signal can also be output to external devices.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Control and Operation of 16-Bit Programmable Timer The following settings must first be made before the 16-bit programmable timer starts counting: 1. Setting pins for input/output (only when necessary) 2. Setting input clock 3. Selecting comparison data register/buffer 4. Setting clock output conditions (signal active level, fine mode) 5. Setting comparison data 6.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS • External clock When using the timer as an event counter by supplying clock pulses from an external source, make sure the event cycle is at least the CPU operating clock period. Selecting comparison data register/buffer The comparison data registers A and B are used to store the data to be compared with the content of the upcounter. This register can be directly read and written. Furthermore, comparison data can be set via the comparison register buffer.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Resetting the counter Each timer includes the PRESETx bit to reset the counter.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Controlling Clock Output The timers can generate a TMx signal using the comparison match signals from the counter. Setting the signal active level By default, an active high signal (normal low) is generated. This logic can be inverted using the OUTINVx bit. When "1" is written to the OUTINVx bit, the timer generates an active low (normal high) signal.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS When OUTINVx = "0" (active high): The timer outputs a low level until the counter becomes equal to the comparison data A set in the CRxA register. When the counter is incremented to the next value from the comparison data A, the output pin goes high and a comparison A interrupt occurs. When the counter becomes equal to the comparison data B set in the CRxB register, the counter is reset and the output pin goes low.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS 16-Bit Programmable Timer Interrupts and DMA The 16-bit programmable timer has a function for generating an interrupt using the comparison match A and B states. The timing at which an interrupt is generated is shown in Figure 4.2 in the preceding section. Control registers of the interrupt controller Table 4.4 shows the control registers of the interrupt controller provided for each timer. Table 4.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS For IDMA to be invoked, the IDMA request and IDMA enable bits shown in Table 4.5 must be set to "1" in advance. Transfer conditions, etc. must also be set on the IDMA side in advance. Table 4.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Trap vectors The trap vector addresses for each default interrupt factor are set as shown below: Timer 0 comparison B: Timer 0 comparison A: Timer 1 comparison B: Timer 1 comparison A: Timer 2 comparison B: Timer 2 comparison A: Timer 3 comparison B: Timer 3 comparison A: Timer 4 comparison B: Timer 4 comparison A: Timer 5 comparison B: Timer 5 comparison A: 0x0C00078 0x0C0007C 0x0C00088 0x0C0008C 0x0C00098 0x0C0009C 0x0C000A8 0x0C000AC 0x0C000B8 0x0C000BC
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS I/O Memory of 16-Bit Programmable Timers Table 4.7 shows the control bits of the 16-bit programmable timers. For details on the I/O memory of the prescaler used to set a clock, refer to "Prescaler". Table 4.7 Control Bits of 16-Bit Programmable Timer Register name Address Bit Setting Init.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Register name Address Bit Name Init. R/W Port input 0–3, high-speed DMA Ch. 0/1, 16-bit timer 0 IDMA request register 0040290 (B) D7 D6 D5 D4 D3 D2 D1 D0 R16TC0 R16TU0 RHDM1 RHDM0 RP3 RP2 RP1 RP0 16-bit timer 0 comparison A 16-bit timer 0 comparison B High-speed DMA Ch.1 High-speed DMA Ch.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Register name Address Port function extension register 00402DF (B) Bit Name Function D7-6 D5 D4 D3 D2 D1 – CFEX5 CFEX4 CFEX3 CFEX2 CFEX1 reserved P05 port extended function P04 port extended function P31 port extended function P21 port extended function P10, P11, P13 port extended function D0 CFEX0 P12, P14 port extended function 1 1 – 1 – 1 #GARD 1 #GAAS 1 DST0 DST1 DPC0 1 DST2 DCLK Setting Init. – – 0 0 0 0 1 – Undefined when read.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Register name Address Bit Name Function Setting Init.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Register name Address Bit Name Function Setting Init.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Register name Address Bit 16-bit timer 3 counter data register 004819C (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC315 TC314 TC313 TC312 TC311 TC310 TC39 TC38 TC37 TC36 TC35 TC34 TC33 TC32 TC31 TC30 16-bit timer 3 counter data TC315 = MSB TC30 = LSB 16-bit timer 3 004819E control register (B) D7 D6 D5 D4 D3 D2 D1 D0 – SELFM3 SELCRB3 OUTINV3 CKSL3 PTM3 PRESET3 PRUN3 reserved 16-bit timer 3 fine mode selection 16-bit timer 3 comparison buf
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Register name Address Bit Name Function Setting Init. 16-bit timer 4 00481A6 control register (B) D7 D6 D5 D4 D3 D2 D1 D0 – SELFM4 SELCRB4 OUTINV4 CKSL4 PTM4 PRESET4 PRUN4 reserved 16-bit timer 4 fine mode selection 16-bit timer 4 comparison buffer 16-bit timer 4 output inversion 16-bit timer 4 input clock selection 16-bit timer 4 clock output control 16-bit timer 4 reset 16-bit timer 4 Run/Stop control – 0 0 0 0 0 0 0 0 – 0 when being read.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS CFP16–CFP10: P1[6:0] pin function selection (D[6:0]) / P1 function select register (0x402D4) Selects the pin to be used for input of an external count clock to the timer. Write "1": Clock input pin Write "0": I/O port pin Read: Valid Select clock input pins for the timers that are used as an event counter from among P10 through P16, by writing "1" to CFP10–CFP16. For the relationship between each pin and timer, refer to Table 4.1.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS SELFM0: Timer 0 SELFM1: Timer 1 SELFM2: Timer 2 SELFM3: Timer 3 SELFM4: Timer 4 SELFM5: Timer 5 fine mode selection (D6) / 16-bit timer 0 control register (0x48186) fine mode selection (D6) / 16-bit timer 1 control register (0x4818E) fine mode selection (D6) / 16-bit timer 2 control register (0x48196) fine mode selection (D6) / 16-bit timer 3 control register (0x4819E) fine mode selection (D6) / 16-bit timer 4 control register (0x481A6) fine mode selection
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS CKSL0: Timer 0 CKSL1: Timer 1 CKSL2: Timer 2 CKSL3: Timer 3 CKSL4: Timer 4 CKSL5: Timer 5 input clock selection (D3) / 16-bit timer 0 control register (0x48186) input clock selection (D3) / 16-bit timer 1 control register (0x4818E) input clock selection (D3) / 16-bit timer 2 control register (0x48196) input clock selection (D3) / 16-bit timer 3 control register (0x4819E) input clock selection (D3) / 16-bit timer 4 control register (0x481A6) input clock sele
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS PRUN0: Timer 0 PRUN1: Timer 1 PRUN2: Timer 2 PRUN3: Timer 3 PRUN4: Timer 4 PRUN5: Timer 5 RUN/STOP control RUN/STOP control RUN/STOP control RUN/STOP control RUN/STOP control RUN/STOP control (D0) / 16-bit timer 0 (D0) / 16-bit timer 1 (D0) / 16-bit timer 2 (D0) / 16-bit timer 3 (D0) / 16-bit timer 4 (D0) / 16-bit timer 5 control control control control control control register (0x48186) register (0x4818E) register (0x48196) register (0x4819E) register (
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS TC015–TC00: Timer 0 TC115–TC10: Timer 1 TC215–TC20: Timer 2 TC315–TC30: Timer 3 TC415–TC40: Timer 4 TC515–TC50: Timer 5 counter counter counter counter counter counter data (D[F:0]) / 16-bit timer 0 counter data register (0x48184) data (D[F:0]) / 16-bit timer 1 counter data register (0x4818C) data (D[F:0]) / 16-bit timer 2 counter data register (0x48194) data (D[F:0]) / 16-bit timer 3 counter data register (0x4819C) data (D[F:0]) / 16-bit timer 4 counter d
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS F16TUx and F16TCx are the interrupt factor flags corresponding to the comparison B and comparison A interrupts, respectively. The flag is set to "1" when each interrupt factor occurs. At this time, if the following conditions are met, an interrupt to the CPU is generated: 1. The corresponding interrupt enable register bit is set to "1". 2. No other interrupt request of a higher priority has been generated. 3.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS DE16TU0, DE16TC0: Timer 0 IDMA enable (D6, D7) / Port input 0–3, HSDMA, 16-bit timer 0 IDMA enable register (0x40294) DE16TU1, DE16TC1: Timer 1 IDMA enable (D0, D1) / 16-bit timer 1–4 IDMA enable register (0x40295) DE16TU2, DE16TC2: Timer 2 IDMA enable (D2, D3) / 16-bit timer 1–4 IDMA enable register (0x40295) DE16TU3, DE16TC3: Timer 3 IDMA enable (D4, D5) / 16-bit timer 1–4 IDMA enable register (0x40295) DE16TU4, DE16TC4: Timer 4 IDMA enable (D6, D7) / 16-b
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS THIS PAGE IS BLANK.
III PERIPHERAL BLOCK: WATCHDOG TIMER III-5 WATCHDOG TIMER Configuration of Watchdog Timer The Periheral Block incorporates a watchdog timer function to detect the CPU's crash. This function is implemented through the use of the 16-bit programmable timer 0. When this function is enabled, an NMI (nonmaskable interrupt) is generated by the comparison B signal from the 16-bit programmable timer 0 (generating intervals can be set through the use of software).
III PERIPHERAL BLOCK: WATCHDOG TIMER Resetting the watchdog timer When using the watchdog timer, prepare a routine to reset the 16-bit programmable timer 0 before an NMI is generated in a location where it will be periodically processed. Make sure this routine is processed within the NMI generation interval described above. The 16-bit programmable timer 0 is reset by writing "1" to PRESET0 (D1) / 16-bit timer 0 control register (0x48186).
III PERIPHERAL BLOCK: WATCHDOG TIMER I/O Memory of Watchdog Timer Table 5.1 shows the control bits of the watchdog timer. Table 5.1 Control Bits of Watchdog Timer Register name Address Setting Init. Watchdog 0040170 timer write(B) protect register D7 WRWD D6–0 – EWD write protection – 1 Write enabled 0 Write-protect – 0 – R/W – 0 when being read. Watchdog timer enable register D7–2 – D1 EWD D0 – – Watchdog timer enable – – 1 NMI enabled 0 NMI disabled – – 0 – – 0 when being read.
III PERIPHERAL BLOCK: WATCHDOG TIMER THIS PAGE IS BLANK.
III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT III-6 LOW-SPEED (OSC1) OSCILLATION CIRCUIT Configuration of Low-Speed (OSC1) Oscillation Circuit The Peripheral Block has a built-in low-speed (OSC1) oscillation circuit. The low-speed (OSC1) oscillation circuit generates a 32.768-kHz (Typ.) subclock. The OSC1 clock output by this circuit is delivered to the CLG (clock generator) in the Core Block and is used as the source clock for the clock timer.
III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT Oscillator Types In the low-speed (OSC1) oscillation circuit, either a crystal oscillation or an external clock input can be selected as the type of oscillation circuit. Figure 6.2 shows the structure of the low-speed (OSC1) oscillation circuit. CG1 OSC1 VDD VSS fOSC1 Rf CD1 VSS X'tal1 OSC2 OSC1 fOSC1 External clock N.C.
III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT Controlling Oscillation The low-speed (OSC1) oscillation circuit can be turned on or off using SOSC1 (D0) / Power control register (0x40180). The oscillation circuit is turned off by writing "0" to SOSC1 and turned back on again by writing "1". SOSC1 is set to "1" at initial reset, so the oscillation circuit is turned on.
III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT Power-Control Register Protection Flag The power-control register (SOSC1, SOSC3, CLKCHG, CLKDT[1:0]) at address 0x40180, which is used to control the oscillation circuits and the CPU operating clock, is normally disabled against writing in order to prevent it from malfunctioning due to unnecessary writing.
III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT I/O Memory of Clock Generator Table 6.3 lists the control bits of clock generator. Table 6.
III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT SOSC1: Low-speed (OSC1) oscillation control (D0) / Power control register (0x40180) Turns the low-speed (OSC1) oscillation on or off. Write "1": OSC1 oscillation turned on Write "0": OSC1 oscillation turned off Read: Valid The oscillation of the low-speed (OSC1) oscillation circuit is stopped by writing "0" to SOSC1, and started again by writing "1".
III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT The following shows the operating status in HALT mode (basic mode and HALT2 mode) and SLEEP mode. Table 6.4 Operating Status in Standby Mode Standby mode HALT mode Basic mode Operating status • • • • • • HALT2 mode • • • • • • SLEEP mode • • • • • The CPU clock is stopped. (CPU stop status) BCU clock is supplied. (BCU run status) DMA clock is not stopped.
III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT CFP14: P14 function selection (D4) / P1 function select register (0x402D4) Selects the pin function of the P14 I/O port. Write "1": OSC1 clock output pin Write "0": I/O port pin Read: Invalid The P14 pin is set for OSC1 clock output (FOSC1) by writing "1" to CFP14. When this pin is used as the FOSC1 output pin, also set IOC14 (D4/0x402D6 ) to "1" (output). At cold start, CFP14 is set to "0" (I/O port pin).
III PERIPHERAL BLOCK: CLOCK TIMER III-7 CLOCK TIMER Configuration of Clock Timer The clock timer consists of an 8-bit binary counter that is clocked by a 256-Hz signal derived from the low-speed (OSC1) oscillation clock fOSC1, and second, minute, hour, and day counters, allowing all data (128 Hz to 1 Hz, seconds, minutes, hours, and day) to be read out in a software.
III PERIPHERAL BLOCK: CLOCK TIMER Control and Operation of the Clock Timer Initial setting At initial reset, the clock timer's counter data, setup contents of alarms, and control bits including RUN/STOP, are not initialized. (This does not include the CPU core power on/off flag TCHVOF or OSC1 auto-off flag TCAOFF.) Therefore, when using the clock timer, initialize it as follows: 1. Before you start setting up, stop the clock timer and disable the clock timer interrupt. 2. Reset the counters. 3.
III PERIPHERAL BLOCK: CLOCK TIMER RUN/STOP the clock timer The clock timer starts counting when "1" is written to TCRUN (D0) / Clock timer Run/Stop register (0x40151) and stops counting when "0" is written. When the clock timer is made to RUN, the 256-Hz clock input is enabled at a falling edge of the low-speed (OSC1) oscillation clock pulse, and the 8-bit binary counter counts up at each falling edge of this 256-Hz clock. Figure 7.2 shows the operation of the 8-bit binary counter.
III PERIPHERAL BLOCK: CLOCK TIMER Setting alarm function The clock timer has an alarm function, enabling an interrupt to be generated at a specified time and day. This specification can be made in minutes, hours, and days for each alarm or a combination of multiple alarms. Use TCASE[2:0] (D[4:2) / Clock timer interrupt control register (0x40152) for this specification. Table 7.
III PERIPHERAL BLOCK: CLOCK TIMER An interrupt can be generated on a specified alarm day at a specified time as described in the preceding section. Interrupts generated by a signal and those generated by an alarm can both be used. However, since the clock timer has only one interrupt factor flag, it is the same interrupt that is generated by the timer.
III PERIPHERAL BLOCK: CLOCK TIMER Examples of Use of Clock Timer The following shows examples of use of the clock timer and how to control the timer in each case. To use the clock timer as a timer/counter Example in which while the CPU is inactive, the clock timer is kept operating in order to start again the CPU after a specified length of time has elapsed (e.g., three days): 1. Make sure the low-speed (OSC1) oscillation circuit is oscillating stably (SOSC1 = "1").
III PERIPHERAL BLOCK: CLOCK TIMER I/O Memory of Clock Timer Table 7.5 shows the control bits of the clock timer. Table 7.5 Control Bits of Clock Timer Register name Address Clock timer Run/Stop register 0040151 (B) Clock timer 0040152 interrupt (B) control register Clock timer 0040153 divider register (B) Clock timer second register Bit Name D7–2 – D1 TCRST D0 TCRUN Function reserved Clock timer reset Clock timer Run/Stop control 1 Reset 1 Run Setting Init. – – X X – 0 when being read.
III PERIPHERAL BLOCK: CLOCK TIMER Register name Address Setting Init. – 0 to 59 minutes (Note) Can be set within 0–63. – X X X X X X – 0 when being read. R/W 004015A D7–5 – (B) D4 TCCD4 D3 TCCD3 D2 TCCD2 D1 TCCD1 D0 TCCD0 reserved – 0 to 23 hours Clock timer hour comparison data (Note) Can be set within 0–31. TCCD4 = MSB TCCD0 = LSB – X X X X X – 0 when being read.
III PERIPHERAL BLOCK: CLOCK TIMER TCRUN: Clock timer RUN/STOP control (D0) / Clock timer Run/Stop register (0x40151) Controls the RUN/STOP of the clock timer. Write "1": RUN Write "0": STOP Read: Valid The clock timer is made to start counting by writing "1" to the TCRUN register and made to stop by writing "0". The timer data is retained even in the STOP state. The timer can also be made to start counting from the retained data by changing its state from STOP to RUN.
III PERIPHERAL BLOCK: CLOCK TIMER TCASE2–TCASE0: Alarm factor select register (D[4:2]) / Clock timer interrupt control register (0x40152) Selects the factor for which an alarm is to be generated. Table 7.7 Selecting Alarm Factor TCASE2 TCASE1 TCASE0 X X 1 0 X 1 X 0 1 X X 0 Alarm factor Minute alarm Hour alarm Day alarm None Use the TCASE2, TCASE1, and TCASE0 bits to select a day, hour, and minute alarm, respectively. It is therefore possible to select multiple alarm factors.
III PERIPHERAL BLOCK: CLOCK TIMER ECTM: Clock timer interrupt enable (D1) / Port input 4–7, clock timer, A/D interrupt enable register (0x40277) Enables or disables generation of an interrupt to the CPU. Write "1": Interrupt enabled Write "0": Interrupt disabled Read: Valid This bit controls the clock timer interrupt. The interrupt is enabled by setting ECTM to "1" and is disabled by setting it to "0". At initial reset, ECTM is set to "0" (interrupt disabled).
III PERIPHERAL BLOCK: CLOCK TIMER Programming Notes (1) The low-speed (OSC1) oscillation circuit, which is the clock source for the clock timer, requires a muxmum of three seconds for its oscillation to stabilize after it is started up. Therefore, immediately after power-on, wait until the oscillation stabilizes before starting the clock timer. (2) At initial reset, the clock timer counter data, the setup contents of alarms, and control bits, including RUN/STOP, are not initialized.
III PERIPHERAL BLOCK: SERIAL INTERFACE III-8 SERIAL INTERFACE Configuration of Serial Interfaces Features of Serial Interfaces The Peripheral Block contains four channels (Ch.0, Ch.1, Ch.2 and Ch.3) of serial interfaces, the features of which are described below. The only differences between these four serial interfaces is that Ch. 1 and Ch. 3 support only asynchronous operation. • A clock-synchronized or asynchronous mode can be selected for the transfer method.
III PERIPHERAL BLOCK: SERIAL INTERFACE I/O Pins of Serial Interface Table 8.1 lists the I/O pins used by the serial interface. Table 8.1 Serial-Interface Pin Configuration Pin name P00/SIN0 I/O Function Function select bit I/O I/O port / Serial IF Ch.0 data input CFP00(D0)/P0 function select register(0x402D0) P01/SOUT0 I/O I/O port / Serial IF Ch.0 data output CFP01(D1)/P0 function select register(0x402D0) P02/#SCLK0 I/O I/O port / Serial IF Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE Method for setting the serial-interface input/output pins All of the pins used in the serial interface are shared with I/O ports. At cold start, they are all set for I/O port pins P0x (function select bit Pxx, CFPxx = "0"). When using the serial interface, make function select bit settings for the pins used, according to the channel and transfer mode to be used. At hot start, the pins retain their status from prior to the reset.
III PERIPHERAL BLOCK: SERIAL INTERFACE Clock-Synchronized Interface Outline of Clock-Synchronized Interface In the clock-synchronized transfer mode, 8 bits of data are synchronized to the common clock on both the transmit and receive sides when the data is transferred. Since the transmit and receive units both have a double-buffer structure, successive transmit and receive operations are possible. Since the clock line is shared between the transmit and receive units, the communication mode is half-duplex.
III PERIPHERAL BLOCK: SERIAL INTERFACE Setting Clock-Synchronized Interface When performing clock-synchronized transfers via the serial interface, the following settings must be made before data transfer is actually begun: 1. Setting input/output pins 2. Setting the interface mode 3. Setting the transfer mode 4. Setting the input clock 5. Setting interrupts and IDMA/HSDMA The following explains the content of each setting.
III PERIPHERAL BLOCK: SERIAL INTERFACE RLD = f PSCIN × pdr - 1 2 × bps (Eq. 1) RLD: Reload data register setup value of the 8-bit programmable timer fPSCIN: Prescaler input clock frequency (Hz) bps: Transfer rate (bits/second) pdr: Division ratio of the prescaler Note: The division ratios selected by the prescaler differ between 8-bit programmable timers 2 and 3, so be careful when setting the ratio.
III PERIPHERAL BLOCK: SERIAL INTERFACE Control and Operation of Clock-Synchronized Transfer Transmit control (1) Enabling transmit operation Use the transmit-enable bit TXENx for transmit control. Ch.0 transmit-enable: TXEN0 (D7) / Serial I/F Ch.0 control register (0x401E3) Ch.1 transmit-enable: TXEN1 (D7) / Serial I/F Ch.1 control register (0x401E8) Ch.2 transmit-enable: TXEN2 (D7) / Serial I/F Ch.2 control register (0x401F3) Ch.3 transmit-enable: TXEN3 (D7) / Serial I/F Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE • Clock-synchronized master mode The timing at which the device starts transmitting in the master mode is as follows: When #SRDY is on a low level while TDBEx = "0" (the transmit-data register contains data written to it) or when TDBEx is set to "0" (data has been written to the transmit-data register) while #SRDY is on a low level. Figure 8.4 shows a transmit timing chart in the clock-synchronized master mode.
III PERIPHERAL BLOCK: SERIAL INTERFACE The #SRDYx signal is returned to a high level at this point. 3. The data in the shift register is shifted 1 bit by the next falling edge of the clock, and the bit following the LSB is output from SOUTx. This operation is repeated until all 8 bits of data are transmitted. 4. The #SRDYx signal is set to a low level when the last bit (8th bit) is output from the SOUTx pin.
III PERIPHERAL BLOCK: SERIAL INTERFACE Ch.0 receive data buffer full: RDBF0 (D0) / Serial I/F Ch.0 status register (0x401E2) Ch.1 receive data buffer full: RDBF1 (D0) / Serial I/F Ch.1 status register (0x401E7) Ch.2 receive data buffer full: RDBF2 (D0) / Serial I/F Ch.2 status register (0x401F2) Ch.3 receive data buffer full: RDBF3 (D0) / Serial I/F Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE 1. After setting the #SRDYx signal to a low level (ready to receive), the slave waits for clock input from the master. 2. The master device outputs each bit of data synchronously with the falling edges of the clock. The LSB is output first. 3. This serial interface takes the SIN input into the shift register at the rising edges of the clock that is input from #SCLKx. The data in the shift register is sequentially shifted as bits are taken in.
III PERIPHERAL BLOCK: SERIAL INTERFACE Asynchronous Interface Outline of Asynchronous Interface Asynchronous transfers are performed by adding a start bit and a stop bit to the start and end points of each serialconverted data. With this method, there is no need to use a clock that is fully synchronized on the transmit and receive sides; instead, transfer operations are timed by the start and stop bits added to the start and end points of each data.
III PERIPHERAL BLOCK: SERIAL INTERFACE Setting Asynchronous Interface When performing asynchronous transfer via the serial interface, the following must be done before data transfer can be started: 1. Setting input/output pins 2. Setting the interface mode 3. Setting the transfer mode 4. Setting the input clock 5. Setting the data format 6. Setting interrupt/IDMA/HSDMA The following describes how to set each of the above.
III PERIPHERAL BLOCK: SERIAL INTERFACE Any desired clock frequency can be obtained by setting the prescaler division ratio and the reload data of the 8-bit programmable timer as necessary. The relationship between the contents of these setting and the transfer rate is expressed by Eq. 2. The 8-bit programmable timer has its underflow signal further divided by 2 internally, in order to ensure that the duty ratio of the clock supplied to the serial interface is 50%.
III PERIPHERAL BLOCK: SERIAL INTERFACE • Sampling clock In the asynchronous mode, TCLK (the clock output by the 8-bit programmable timer or input from the #SCLKx pin for Ch. 0 and Ch. 2) is internally divided in the serial interface, in order to create a sampling clock. A 1/16 division ratio is selected by writing "0" to DIVMDx , and a 1/8 ratio is selected by writing "1". Ch.0 clock division ratio selection: DIVMD0 (D4) / Serial I/F Ch.0 IrDA register (0x401E4) Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE Setting the data format In the asynchronous mode, the data length is 7 or 8 bits as determined by the transfer mode set. The start bit is fixed at 1. The stop and parity bits can be set as shown in the Table 8.5 using the following control bits: Table 8.5 Serial I/F Control Bits Ch.0 (Serial I/F Ch.0 Ch.1 (Serial I/F Ch.1 Ch.2 (Serial I/F Ch.2 control register) control register) control register) Ch.3 (Serial I/F Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE The transfer status can be checked using the transmit-completion flag (TENDx). Ch.0 transmit-completion flag: TEND0 (D5) / Serial I/F Ch.0 status register (0x401E2) Ch.1 transmit-completion flag: TEND1 (D5) / Serial I/F Ch.1 status register (0x401E7) Ch.2 transmit-completion flag: TEND2 (D5) / Serial I/F Ch.2 status register (0x401F2) Ch.3 transmit-completion flag: TEND3 (D5) / Serial I/F Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE Receive control (1) Enabling receive operations Use the receive-enable bit RXENx for receive control. Ch.0 receive-enable: RXEN0 (D6) / Serial I/F Ch.0 control register (0x401E3) Ch.1 receive-enable: RXEN1 (D6) / Serial I/F Ch.1 control register (0x401E8) Ch.2 receive-enable: RXEN2 (D6) / Serial I/F Ch.2 control register (0x401F3) Ch.3 receive-enable: RXEN3 (D6) / Serial I/F Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE Note: The receive operation is terminated when the first stop bit is sampled even if the stop bit is configured with two bits. • Successive receive operations When the data received in the shift register is transferred to the receive data register, RDBFx is set to "1" (buffer full), indicating that the received data can be read out. Thereafter, data can be received successively because the receive data register can be read out while the next data is received.
III PERIPHERAL BLOCK: SERIAL INTERFACE • Overrun error If during successive receive operations, a receive operation for the next data is completed before the receive data register is read out, the receive data register is overwritten with the new data. Therefore, the receive data register must always be read out before a receive operation for the next data is completed. When the receive data register is overwritten, an overrun error is generated and the overrun-error flag is set to "1". Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE IrDA Interface Outline of IrDA Interface Each channel of the serial interface contains a PPM modulator circuit, allowing an infrared-ray communication circuit to be configured based on IrDA 1.0 simply by adding a simple external circuit. Infrared communication module S1C33 LED A PPM Modulator SOUTx LED TXD VP1N LED C Serial I/F Photodiode PPM Modulator SINx RXD CX1 VDD Vcc CX2 VSS VP1N GND (Example: HP HSDL-1000) Figure 8.
III PERIPHERAL BLOCK: SERIAL INTERFACE Selecting the IrDA interface function To use the IrDA interface function, select it using the control bits shown below and then set the 8-bit (or 7-bit) asynchronous mode as the transfer mode. Ch.0 IrDA interface-function selection: IRMD0[1:0] (D[1:0]) / Serial I/F Ch.0 IrDA register (0x401E4) Ch.1 IrDA interface-function selection: IRMD1[1:0] (D[1:0]) / Serial I/F Ch.1 IrDA register (0x401E9) Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE Control and Operation of IrDA Interface The transmit/receive procedures have been explained in the section on the asynchronous interface, so refer to "Control and Operation of Asynchronous Transfer". The following describes the data modulation and demodulation performed using the PPM modulator circuit: When transmitting During data transmission, the pulse width of the serial interface output signal is set to 3/16 before the signal is output from the SOUTx pin.
III PERIPHERAL BLOCK: SERIAL INTERFACE Serial Interface Interrupts and DMA The serial interface can generate the following three types of interrupts in each channel: • Transmit-buffer empty interrupt • Receive-buffer full interrupt • Receive-error interrupt Transmit-buffer empty interrupt factor This interrupt factor occurs when the transmit data set in the transmit data register is transferred to the shift register, in which case the interrupt factor flag FSTXx is set to "1".
III PERIPHERAL BLOCK: SERIAL INTERFACE The interrupt priority register sets the interrupt priority level of each interrupt source in a range between 0 and 7. An interrupt request to the CPU is accepted only when no other interrupt request of a higher priority has been generated.
III PERIPHERAL BLOCK: SERIAL INTERFACE If an interrupt factor occurs when the IDMA request and enable bits are set to "1", IDMA is invoked. No interrupt request is generated at that point. An interrupt request is generated upon completion of the DMA transfer. The bits can also be set so as not to generate an interrupt, with only a DAM transfer performed. For details on DMA transfer and how to control interrupts upon completion of DMA transfer, refer to "IDMA (Intelligent DMA)". • Ch.2 and Ch.3 For Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE • Ch.2 and Ch.3 For Ch.2 and Ch.3, either port input interrupts or 16-bit timer interrupts are selected, and HSDMA is invoked by means of those interrupt factor (See Table 8.10). When port input interrupts are selected, Serial I/F Ch.2 receive buffer full corresponds to port 1, and transmit buffer empty to port 3. Therefore, HSDMA can be invoked by setting HSDMA Ch.1 and Ch.3 trigger factor values (D[7:4]/0x40298, D[7:4]/0x40299) of "0011".
III PERIPHERAL BLOCK: SERIAL INTERFACE I/O Memory of Serial Interface Table 8.14 shows the control bits of the serial interface. For details on the I/O memory of the prescaler that is used to set clocks, as well of that of 8-bit programmable timers, refer to "Prescaler" and "8-Bit Programmable Timers", respectively. Table 8.14 Name Control Bits of Serial Interface Register name Address Bit Function Setting Init. Serial I/F Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE Register name Address Bit Name Function Serial I/F Ch.1 00401E7 D7–6 – status register (B) D5 TEND1 D4 FER1 D3 PER1 D2 OER1 D1 TDBE1 D0 RDBF1 – Ch.1 transmit-completion flag Ch.1 flaming error flag Ch.1 parity error flag Ch.1 overrun error flag Ch.1 transmit data buffer empty Ch.1 receive data buffer full Serial I/F Ch.1 00401E8 control register (B) Ch.1 transmit enable Ch.1 receive enable Ch.1 parity enable Ch.1 parity mode selection Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE Register name Address Bit Setting Init. R/W Serial I/F Ch.3 transmit data register 00401F5 (B) D7 D6 D5 D4 D3 D2 D1 D0 TXD37 TXD36 TXD35 TXD34 TXD33 TXD32 TXD31 TXD30 Serial I/F Ch.3 transmit data TXD37(36) = MSB TXD30 = LSB 0x0 to 0xFF(0x7F) X X X X X X X X R/W Serial I/F Ch.3 receive data register 00401F6 (B) D7 D6 D5 D4 D3 D2 D1 D0 RXD37 RXD36 RXD35 RXD34 RXD33 RXD32 RXD31 RXD30 Serial I/F Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE Register name Address Bit Serial I/F 0040286 interrupt factor (B) flag register D7–6 D5 D4 D3 D2 D1 D0 – FSTX1 FSRX1 FSERR1 FSTX0 FSRX0 FSERR0 Name reserved SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full SIF Ch.1 receive error SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full SIF Ch.0 receive error Function Setting Init. – – X X X X X X – 0 when being read.
III PERIPHERAL BLOCK: SERIAL INTERFACE Register name Address P0 function select register 00402D0 (B) Port SIO function extension register Bit D7-6 D5 D4 D3 D2 D1 D0 Name Function Reserved P05 function selection P04 function selection P03 function selection P02 function selection P01 function selection P00 function selection 1 1 1 1 1 1 00402D7 D7–4 – D3 CFP322 reserved P32 function selection 2 1 – D2 CFP152 P15 function selection 2 1 – D1 CFP162 P16 function selection 2 1 – D0 CFP3
III PERIPHERAL BLOCK: SERIAL INTERFACE CFP162: P16 function selection 2 (D1) / Port SIO function extension register (0x402D7) Specifies the function of pin P16/EXCL5/#DMAEND1. Always set to "0." Write "0": P16/EXCL5/#DMAEND1 Read: Valid To use the pin as P16, EXCL5, or #DMAEND1, set this bit to "0". At power-on, this bit is set to "0". CFP152: P15 function selection 2 (D2) / Port SIO function extension register (0x402D7) Specifies the function of pin P15/EXCL4/#DMAEND0. Always set to "0.
III PERIPHERAL BLOCK: SERIAL INTERFACE SSCLK2: Serial I/F Ch.2 SCLK selection (D2) / Port SIO function extension register (0x402DB) Switches the function of pin P25/TM3/#SCLK2. Write "1": #SCLK2 Write "0": P25/TM3 Read: Valid To use the pin as #SCLK2, set SSCLK2 (D2 / 0x402DB) to "1" and CFP25 (D5 / 0x402D8) to "0". To use the pin as P25 or TM3, set this bit to "0". At power-on, this bit is set to "0". SSRDY2: Serial I/F Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE RXD07–RXD00: Ch.0 RXD17–RXD10: Ch.1 RXD27–RXD20: Ch.2 RXD37–RXD30: Ch.3 receive receive receive receive data (D[7:0]) / Serial I/F Ch.0 data (D[7:0]) / Serial I/F Ch.1 data (D[7:0]) / Serial I/F Ch.2 data (D[7:0]) / Serial I/F Ch.3 receive receive receive receive data register (0x401E1) data register (0x401E6) data register (0x401F1) data register (0x401F6) Stores received data.
III PERIPHERAL BLOCK: SERIAL INTERFACE PER0: Ch.0 PER1: Ch.1 PER2: Ch.2 PER3: Ch.3 parity-error flag (D3) / Serial I/F Ch.0 status register (0x401E2) parity-error flag (D3) / Serial I/F Ch.1 status register (0x401E7) parity-error flag (D3) / Serial I/F Ch.2 status register (0x401F2) parity-error flag (D3) / Serial I/F Ch.3 status register (0x401F7) Indicates whether a parity error occurred.
III PERIPHERAL BLOCK: SERIAL INTERFACE RDBF0: Ch.0 RDBF1: Ch.1 RDBF2: Ch.2 RDBF3: Ch.3 receive receive receive receive data buffer data buffer data buffer data buffer full (D0) / Serial I/F Ch.0 full (D0) / Serial I/F Ch.1 full (D0) / Serial I/F Ch.2 full (D0) / Serial I/F Ch.3 status status status status register (0x401E2) register (0x401E7) register (0x401F2) register (0x401F7) Indicates the status of the receive data register (buffer).
III PERIPHERAL BLOCK: SERIAL INTERFACE EPR0: Ch.0 EPR1: Ch.1 EPR2: Ch.2 EPR3: Ch.3 parity enable parity enable parity enable parity enable (D5) / Serial I/F Ch.0 (D5) / Serial I/F Ch.1 (D5) / Serial I/F Ch.2 (D5) / Serial I/F Ch.3 control control control control register (0x401E3) register (0x401E8) register (0x401F3) register (0x401F8) Selects a parity function.
III PERIPHERAL BLOCK: SERIAL INTERFACE SSCK0: Ch.0 SSCK1: Ch.1 SSCK2: Ch.2 SSCK3: Ch.3 input clock selection (D2) / Serial I/F Ch.0 control register (0x401E3) input clock selection (D2) / Serial I/F Ch.1 control register (0x401E8) input clock selection (D2) / Serial I/F Ch.2 control register (0x401F3) input clock selection (D2) / Serial I/F Ch.3 control register (0x401F8) Selects the clock source for an asynchronous transfer.
III PERIPHERAL BLOCK: SERIAL INTERFACE IRTL0: Ch.0 IRTL1: Ch.1 IRTL2: Ch.2 IRTL3: Ch.3 IrDA output logic inversion (D3) / Serial I/F Ch.0 IrDA register (0x401E4) IrDA output logic inversion (D3) / Serial I/F Ch.1 IrDA register (0x401E9) IrDA output logic inversion (D3) / Serial I/F Ch.2 IrDA register (0x401F4) IrDA output logic inversion (D3) / Serial I/F Ch.3 IrDA register (0x401F9) Inverts the logic of the IrDA output signal.
III PERIPHERAL BLOCK: SERIAL INTERFACE ESERR0, ESRX0, ESTX0: Ch.0 interrupt enable (D0,D1,D2) / Serial I/F interrupt enable register (0x40276) ESERR1, ESRX1, ESTX1: Ch.1 interrupt enable (D3,D4,D5) / Serial I/F interrupt enable register (0x40276) Enable or disable interrupt generation to the CPU.
III PERIPHERAL BLOCK: SERIAL INTERFACE RSRX0, RSTX0: Ch.0 IDMA request (D6, D7) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA request register (0x40292) RSRX1, RSTX1: Ch.1 IDMA request (D0, D1) / Serial I/F Ch.1, A/D IDMA request register (0x40293) Specifies whether to invoke IDMA when an interrupt factor occurs.
III PERIPHERAL BLOCK: SERIAL INTERFACE SIO2RS0: SIO Ch.2 receive-buffer full/FP1 interrupt factor switching (D1) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": SIO Ch.2 receive-buffer full Write "0": FP1 input Read: Valid Set to "1" to use the SIO Ch.2 receive-buffer full interrupt. Set to "0" to use the FP1 input interrupt. At power-on, this bit is set to "0". SIO3ES0: SIO Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE SIO3TS0: SIO Ch.3 transmit-buffer empty/FP6 interrupt factor switching (D6) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": SIO Ch.3 transmit-buffer empty Write "0": FP6 input Read: Valid Set to "1" to use the SIO Ch.3 transmit-buffer empty interrupt. Set to "0" to use the FP6 input interrupt. At power-on, this bit is set to "0".
III PERIPHERAL BLOCK: SERIAL INTERFACE SIO3TS1: SIO Ch.3 transmit-buffer empty/TM16 Ch.4 compare A interrupt factor switching (D3) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. Write "1": SIO Ch.3 transmit-buffer empty Write "0": TM16 Ch.4 compare A Read: Valid Set to "1" to use the SIO Ch.3 transmit-buffer empty interrupt. Set to "0" to use the TM16 Ch.4 compare A interrupt. At power-on, this bit is set to "0". SIO2ES1: SIO Ch.2 receive error/TM16 Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE Programming Notes (1) Before setting various serial-interface parameters, make sure the transmit and receive operations are disabled (TXENx = RXENx = "0"). (2) When the serial interface is transmitting or receiving data, do not set TXENx or RXENx to "0", and do not execute the slp instruction. (3) In clock-synchronized transfers, the mode of communication is half-duplex, in which the clock line is shared between the transmit and receive units.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS III-9 INPUT/OUTPUT PORTS The Peripheral Block has a total of 42 input/output ports. Although each pin is used for input/output from/to the internal peripheral circuits, some pins can be used as general-purpose input/output ports unless they are used for the peripheral circuits. Input Ports (K Ports) Structure of Input Port The Peripheral Block contains 7 bits of input ports (K50 to K52, K60 to K63). Figure 9.1 shows the structure of a typical input port.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Input-Port Pins The input pins concurrently serve as the input pins for peripheral circuits, as shown in Table 9.1. Whether they are used as input ports or for peripheral circuits can be set bit-for-bit using a function select register. All pins not used for peripheral circuits can be used as general-purpose input ports that have an interrupt function. Table 9.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS I/O Memory of Input Ports Table 9.2 shows the control bits of the input ports. Table 9.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS I/O Ports (P Ports) Structure of I/O Port The Peripheral Block contains 29 bits of I/O ports (P00 to P05, P10 to P16, P20 to P27, P30 to P35) that can be directed for input or output through the use of a program. Figure 9.2 shows the structure of a typical I/O port. VDDE Internal data bus I/O control register Function select register Pxx Data register Peripheral circuit output VSS Peripheral circuit input Figure 9.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Pin name P20/#DRD P21/#DWE/ #GAAS P22/TM0 P23/TM1 P24/TM2/ #SRDY2 P25/TM3/ #SCLK2 P26/TM4/ SOUT2 P27/TM5/SIN2 P30/#WAIT/ #CE4&5 P31/#BUSGET/ #GARD P32/#DMAACK0 P33/#DMAACK1 P34/#BUSREQ/ #CE6 P35/#BUSACK I/O Pull-up Function I/O – I/O port / #DRD output I/O – I/O port / #DWE output / GA address strobe output (Ex) I/O – I/O port / 16-bit timer 0 output I/O – I/O port / 16-bit timer 1 output I/O – I/O port / 16-bit timer 2 output / Serial IF Ch.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS I/O Memory of I/O Ports Table 9.4 shows the control bits of the I/O ports. Table 9.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Register name Address Port SIO function extension register Bit Name Function Setting Init. – – 0 – R/W Always set to 0. 0 R/W Always set to 0. 0 R/W Always set to 0. 0 R/W Always set to 0. P27 P26 P25 P24 P23 P22 P21 P20 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Ext. func.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Register name Address Port function extension register 00402DF (B) Bit Name Function D7-6 D5 D4 D3 D2 D1 – CFEX5 CFEX4 CFEX3 CFEX2 CFEX1 reserved P05 port extended function P04 port extended function P31 port extended function P21 port extended function P10, P11, P13 port extended function D0 CFEX0 P12, P14 port extended function CFP05–CFP00: P0[5:0] CFP16–CFP10: P1[6:0] CFP27–CFP20: P2[7:0] CFP35–CFP30: P3[5:0] function selection function selection fun
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS IOC05–IOC00: P0[5:0] port I/O IOC16–IOC10: P1[6:0] port I/O IOC27–IOC20: P2[7:0] port I/O IOC35–IOC30: P3[5:0] port I/O control (D[5:0]) / P0 port I/O control register (0x402D2) control (D[6:0]) / P1 port I/O control register (0x402D6) control (D[7:0]) / P2 port I/O control register (0x402DA) control (D[5:0]) / P3 port I/O control register (0x402DE) Directs an I/O port for input or output.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS CFEX0: P12, P14 function extension (D0) / Port function extension register (0x402DF) CFEX1: P10, P11, P13 function extension (D1) / Port function extension register (0x402DF) CFEX2: P21 function extension (D2) / Port function extension register (0x402DF) CFEX3: P31 function extension (D3) / Port function extension register (0x402DF) CFEX4: P04 function extension (D4) / Port function extension register (0x402DF) CFEX5: P05 function extension (D5) / Port function exte
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Input Interrupt The input ports and the I/O ports support eight system of port input interrupts and two systems of key input interrupts. Port Input Interrupt The port input interrupt circuit has eight interrupt systems (FPT7–FPT0) and a port can be selected for generating each interrupt factor. The interrupt condition can also be selected from between input signal edge and input signal level. Figure 9.3 shows the configuration of the port input interrupt circuit.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Conditions for port input-interrupt generation Each port input interrupt can be generated by the edge or level of the input signal. The SEPTx bit of the edge/level select register (0x402C9) is used for this selection. When SEPTx is set to "1", the FPTx interrupt will be generated at the signal edge. When SEPTx is set to "0", the FPTx interrupt will be generated by the input signal level.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Key Input Interrupt The key input interrupt circuit has two interrupt systems (FPK1 and FPK0) and a port group can be selected for generating each interrupt factor. The interrupt condition can also be set by software. Figure 9.4 shows the configuration of the port input interrupt circuit.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Selecting input pins For the FPK1 interrupt system, a four-bit input pin group can be selected from the four predefined groups. For the FPK0 system, a five-bit input pin group can be selected. Table 9.7 shows the control bits and the selectable groups for each factor. Table 9.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Since K50 is masked from interrupt by SMPK00, no interrupt occurs at that point (2) above. Next, because CP4 becomes "0" at (3), an interrupt is generated due to the lack of a match between the data of the input pins K5[2:1] and CP4 that are enabled for interrupt and that of the input comparison register SCPK0[4:1].
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Table 9.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS I/O Memory for Input Interrupts Table 9.10 shows the control bits for the port input and key input interrupts. Table 9.10 Bit Setting Init. Port input 0/1 0040260 interrupt (B) priority register D7 D6 D5 D4 D3 D2 D1 D0 – PP1L2 PP1L1 PP1L0 – PP0L2 PP0L1 PP0L0 reserved Port input 1 interrupt level – 0 to 7 – 0 when being read.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Register name Address Bit Port input 4–7, 0040287 clock timer, A/D (B) interrupt factor flag register D7–6 D5 D4 D3 D2 D1 D0 Name Function – FP7 FP6 FP5 FP4 FCTM FADE reserved Port input 7 Port input 6 Port input 5 Port input 4 Clock timer A/D converter Setting Init. – – X X X X X X – 0 when being read. R/W R/W R/W R/W R/W R/W 1 Factor is generated 0 No factor is generated R/W Remarks Port input 0–3, high-speed DMA Ch.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Function Setting Init. Key input 00402CA D7–4 – interrupt select (B) D3 SPPK11 register D2 SPPK10 D1 SPPK01 D0 SPPK00 Register name Address Bit Name reserved FPK1 interrupt input port selection – – 0 0 0 0 – 0 when being read.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS SPPT7–SPPT0: Input polarity selection (D[7:0]) / Port interrupt input polarity select register (0x402C8) Selects input signal porarity for port interrupt generation. Write "1": High level or Rising edge Write "0": Low level or Falling edge Read: Valid SPPTx is the input polarity select bit corresponding to the FPTx interrupt. When SPPTx is set to "1", the FPTx interrupt will be generated by a high level input or at the rising edge.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS SMPK13–SMPK10: FPK1 input mask (D[3:0]) / FPK1 input mask register (0x402CF) SMPK04–SMPK00: FPK0 input mask (D[4:0]) / FPK0 input mask register (0x402CE) Sets conditions for key-input interrupt generation (interrupt enabled/disabled). Write "1": Interrupt enabled Write "0": Interrupt disabled Read: Valid SMPK is an input mask register for each key-input interrupt system. Interrupts for bits set to "1" are enabled, and interrupts for bits set to "0" are disabled.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS FP3–FP0: Port input 3–0 interrupt factor flag (D[3:0]) / Key input, port input 0–3 interrupt factor flag register (0x40280) FP7–FP4: Port input 7–4 interrupt factor flag (D[5:2]) / Port input 4–7, clock timer, A/D interrupt factor flag register (0x40287) FK1, FK0: Key input 1, 0 interrupt factor flag (D[5:4]) / Key input, port input 0–3 interrupt factor flag register (0x40280) Indicates the status of an input interrupt factor generated.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS RP3–RP0: Port input 3–0 IDMA request (D[3:0]) / Port input 0–3, high-speed DMA, 16-bit timer 0 IDMA request register (0x40290) RP7–RP4: Port input 7–4 IDMA request (D[7:4]) / Serial I/F Ch.1, A/D, Port input 4–7 IDMA request register (0x40293) Specifies whether to invoke IDMA when an interrupt factor occurs.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS (5) When a port input interrupt is used to trigger a restart from HALT2 mode or SLEEP mode, the interrupt will be generated by level detection, even if edge detection is set up. See the "Programming Notes" in the Core Block CLG section for details.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES III-10 Monitored Mobile Access Interfaces Configuration of Mobile Access Interfaces Features The C33 peripheral block includes mobile access interfaces with the following features. Used in combination with the software modem module, they support data communications with PDC, packet PDC, PHS, and CdmaOne mobile devices. • • • • • • There are four configuration choices.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES I/O Pins for Mobile Access Interfaces Table 10.1 lists the I/O pins for the mobile access interfaces. Table 10.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES CTS (CTS input pin) The function of this input pin depends on the communications mode. UART communications interprets this input as the CTS signal from the mobile device. A bit in the communications block modem status register (0x020002A) tracks the input level. Note that there is no hardware flow control. HDLC communications feeds this bit clock signal to the packet processor block.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES List of Pin Functions Table 10.2 lists the five mobile access interface pin configurations specified by the MSEL pin input level and communications macro select (MCRS) register (D[1:0]/0x200000). Pin Name DTR RTS TXD RI CTS DCD DSR RXD CNT1 CNT2 GOUT I/O O O O I I I I I O O O Table 10.2 Mobile Access Interface Pin Configurations MSEL = Low MSEL = High Communications Mode Serial IF Ch.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES Communications Mode Next configure the mobile access interface pins with the MSEL pin input level and communications macro select (MCRS) register (D[1:0]/0x200000). (See Table 10.4.) The default MCRS setting, after an initial reset, is 00, which specifies UART or serial IF Ch. 3. MSEL Input Level High MCRS1 High 1 High 0 High 0 Low 0 1 Table 10.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES 64 kbps: 10 ms PIAFS frame period 5 ms Frame signal period 5 ms DCD (frame signal) CTS (bit clock, 64 kHz) 0 1 2 3 4 5 6 7 8 9 TXD and RXD (data signals) (Total 640 bits) Figure 10.3 PHS Signal Format (2) 32 kbps: 20 ms PIAFS frame period 125 µs 125 µs 125 µs Frame signal period DCD (frame signal) CTS (bit clock, 32 kHz) TXD and RXD (data signals) 0 1 2 3 4 5 6 7 8 9 (Total 640 bits) Figure 10.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES 32 kbps: 20 ms PIAFS frame period 125 µs 125 µs Frame signal period DCD (frame signal) CTS (bit clock, 64 kHz) TXD and RXD (data signals) 0 1 2 3 * * * * 4 5 6 7 * * * * 8 9 (Total 640 bits) Note: * These bits are "1" for output. Their value does not matter for input. Figure 10.6 PHS Signal Format (5) UART Communications Mode Overview UART communications data transfers use serial IF Ch. 3 asynchronous operation.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES PDC Communications Mode Overview The PDC communications mode works in combination with the software modem module to process ARQ frames for data transfers with PDC devices. For a transmit operation, this mode serially transmits 24 bytes of data from one of two buffers plus two 16-bit CRCs using the frame and clock timing from the PDC device.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES bit 7 ¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥ 0x0200580 0x020057E Receive Buffer B (32 bytes) 0x0200540 0x020053E Receive Buffer A (32 bytes) 0x0200500 0x02004FE 0x0200480 0x020047E Transmit Buffer B (32 bytes) 0x0200440 0x020043E Transmit Buffer A (32 bytes) 0x0200400 Figure 10.8 PDC Communications Mode Data Buffers CRC Checking PDC communications uses the following two CRC polynomials for validating frame data integrity. Figure 10.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES PDC Communications Control and Operation Transmit Control (1) Enabling transmit operation Setting the transmit enable (TXEN) bit in the PDC command register (D1/0x0200102) to "1" enables transmit operation, starting transmission from the start of the specified transmit buffer at the next falling edge in the PDC frame signal. (2) Procedure There are two 32-byte transmit data buffers.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES PHS Communications Mode Overview The PHS communications mode works in combination with the software modem module to process PIAFS frames for data transfers with PHS devices. For a transmit operation, this mode serially transmits 76 bytes of data from one of two buffers plus a 32-bit CRC using the frame and clock timing from the PHS device.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES Data Buffers PHS communications uses two 80-byte buffers each for transmitting and receiving. Transmit operation uses only the 76 bytes at the start of a buffer; receive operation, all 80. The transmit buffers are write only; the receive buffers, read only.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES PHS Communications Control and Operation Transmit Control (1) Enabling transmit operation Setting the transmit enable (TXEN) bit in the PHS command register (D0/0x0200200) to "1" enables transmit operation, starting transmission from the start of the specified transmit buffer using the PHS clock timing. (2) Procedure There are two 80-byte transmit data buffers.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES HDLC Communications Mode Overview The HDLC communications mode processes HDLC frames for data transfers with PDC devices supporting packets. For a transmit operation, this mode transmits an opening flag pattern, the data from a built-in 8-bit, 4-stage queue (LSB first), a CRC, and a closing flag pattern. Outside flag patterns, the hardware automatically inserts a "0" after six "1" bits in a row.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES HDLC Communications Control and Operation Transmit Control (1) Enabling transmit operation Setting the transmit enable (TXENS) bit in the HDLC command register (D6/0x0200308) to "1" enables transmit operation, starting transmission from the start of the specified transmit queue using the HDLC clock timing. (2) Basic Procedure Write the address, control, and data fields to the HDLC transmit data register (0x020031E).
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES If the enable bit in the HDLC receive operation settings register (D7/0x020030E) specifies address comparison, the hardware rejects frames whose address fields do not match the contents of the receive address register. Otherwise, it accepts them all.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES (2) (3) HDLC Receive Interrupts (Rx INT) The Rx INT and Sp INT interrupt request timing depends on the receive interrupt setup setting in the HDLC receive interrupt mode settings register (D[1:0]/0x0200312).
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES Mobile Access Interface Interrupts Overview The mobile access interface module generates eight interrupt requests, mapped according to the communications mode under program control to five interrupt request lines to the CPU core. Interrupt Types Table 10.8 lists the interrupt requests for each communications mode. Communications mode PDC communications mode PHS communications mode HDLC communications mode All communications modes Symbol Table 10.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES (5) TXINT = HDLC transmit interrupt Interrupt source The data in the transmit queue or transmit block satisfies the conditions below. Condition 1. The software has not written data for the next frame by the time that the interface sends the second CRC byte. 2. The software has filled the transmit queue above the threshold before the interface sends the second CRC byte. To clear Write "1" to the reset TXINT bit (6) SPINT = HDLC Sp interrupt A.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES D. Interrupt source: Idle detect Condition The signal latched into the idle detect changes from "0" to "1." To clear Reset E/S INT command (8) MSINT = Modem status change interrupt Interrupt source Change in modem status input signals Condition The RI, CTS, DCD, or DSR input signal changes (either direction).
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES I/O Memory for Mobile Access Interfaces Table 10.11 lists the contents of the I/O memory for mobile access interfaces. Table 10.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES Name Function Communications 0200026 D15–5 – block CP3 (HW) D4 CP3EN4 interrupt select D3 CP3EN3 register D2 CP3EN2 D1 CP3EN1 D0 CP3EN0 Register name Address Bit – Assign UINT4 to CP3 Assign UINT3 to CP3 Assign UINT2 to CP3 Assign UINT1 to CP3 Assign UINT0 to CP3 1 1 1 1 1 Enable Enable Enable Enable Enable Communications 0200028 D15–5 – block CP4 (HW) D4 CP4EN4 interrupt select D3 CP4EN3 register D2 CP4EN2 D1 CP4EN1 D0 CP4EN0 – Map UINT4 in
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES Register name Address PHS receive status register Bit Name 0200206 D15–8 – (HW) D7 RXINT D6–3 – D2 CRCER D1 RXBS D0 – Function Setting – PHS receive interrupt flag – PHS receive data CRC-32 error flag PHS receive buffer select – – 1 Request pending 0 No interrupts – 1 CRC error 0 No error 1 Buffer B 0 Buffer A – – 0 – X X – – R/W – R R – 0 when being read. Write "1" to clear 0 when being read. – – W W – W W 0 when being read.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES Register name Address Bit Name Function Setting Init. R/W – HDLC receive interrupt setup HDLC receive 0200314 D15–3 – control register (HW) D2 RXFR D1 ENTHM D0 RXINXT – – 1 Reset 0 Ignored HDLC receive queue reset 1 Force shift 0 Ignored HDLC enter Hunt mode HDLC Rx INT on next receive character 1 Specify interrupt 0 Ignored – 0 0 0 – W W W 0 when being read.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES Register name Address HDLC residue code register Bit Name 0200332 D15–8 – (HW) D7 RCODE7 D6 RCODE6 D5 RCODE5 D4 RCODE4 D3 RCODE3 D2 RCODE2 D1 RCODE1 D0 RCODE0 Function RCODE[7:0] 11111110 11111100 11111000 11110000 11100000 11000000 10000000 HDLC transmit 0200334 D15–8 – status register (HW) D7 TXUE D6 TXBRDY D5–1 – D0 TXUDR – HDLC Tx underrun/EOM HDLC transmit buffer ready – HDLC Tx underrun HDLC monitor register – HDLC E/S INT monitored HD
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES BMODE, BHALF, FMODE: PHS signal format (D[2:0]) / Communications block PHS mode settings register (0x0200010) These bits specify the interface signal format for PHS communications. They are ignored for other communications modes. Use only the combinations given. BMODE BHALF FMODE 0 0 0 1 0 1 1 1 1 Table 10.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES CNT2, CNT1: Output port data (D[1:0]) /Communications block output port data register (0x020000A) Regardless of the communications macro select (MCRS) register (D[1:0]/0x200000) setting–that is, in all modes– these bits drive the CNT2 and CNT1 output pins using negative logic. (See Table.) Table 10.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES SDRI, SURI, SDCTS, SUCTS, SDDCD, SUDCD, SDDSR, SUDSR: Modem status (D[7:0]) / Communications block modem status register (0x020002A) For reads, these bit pairs indicate changes in the input level for the corresponding status bit.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES INTE: PDC interrupt enable (D1) / PDC interrupt register (0x0200100) PDCINT: PDC interrupt flag(D0) / PDC interrupt register (0x0200100) These bits respectively control and indicate the PDC interrupt requests to the CPU every 20 ms at the falling edge of the frame signal from the PDC device. Setting INTE to "1" enables these interrupts that generate every 20 ms at the falling edge of the frame signal from the PDC device.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES TXINTE: PHS transmit interrupt enable (D7) / PHS transmit control register (0x0200200) TXBS: PHS transmit buffer select (D1) / PHS transmit control register (0x0200200) TXEN: PHS transmit enable (D0) / PHS transmit control register (0x0200200) These bits control PHS transmit operation. The hardware latches the register contents at the PHS transmit interrupt, so update these bits between one such interrupt request and the next.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES RXINT: PHS receive interrupt flag (D7) / PHS receive status register (0x0200206) CRCER: PHS receive data CRC-32 error flag (D2) / PHS receive status register (0x0200206) RXBS: PHS receive buffer select (D1) / PHS receive status register (0x0200206) These bits indicate the status of PHS receive operation.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES ABRTIES: HDLC enable TXUEIES: HDLC enable (0x0200304) HUNTIES HDLC enable IDLDIES: HDLC enable (0x0200304) bit for Abort (D7) / HDLC interrupt enable settings register (0x0200304) bit for Tx underrun/EOM (D6) / HDLC interrupt enable settings register bit for Hunt (D5) / HDLC interrupt enable settings register (0x0200304) bit for idle detect conditions (D4) / HDLC interrupt enable settings register Writing "1" to a bit enables E/S INT interrupts for
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES ABRTIEC: HDLC clear enable TXUEIEC: HDLC clear enable (0x0200306) HUNTIEC: HDLC clear enable IDLDIEC: HDLC clear enable (0x0200306) bit for Abort (D7) / HDLC clear interrupt enable register (0x0200306) bit for Tx underrun/EOM (D6) / HDLC clear interrupt enable register bit for Hunt(D5) / HDLC clear interrupt enable register (0x0200306) bit for idle detect conditions(D4) / HDLC clear interrupt enable register Writing "1" to a bit disables E/S INT in
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES RXENS: TXENS: RXIES: TXIES: HDLC receive enable (D7) / HDLC transfer settings register (0x0200308) HDLC transmit enable (D6) / HDLC transfer settings register (0x0200308) HDLC Rx and Sp INT enable (D1) / HDLC transfer settings register (0x0200308) HDLC Tx INT enable (D0) / HDLC transfer settings register (0x0200308) Writing "1" to a bit enables the corresponding operation or interrupts. Writes of "0" are ignored.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES RXENC: HDLC clear receive enable (D7) / HDLC cancel transfer register (0x020030A) TXENC: HDLC clear transmit enable (D6) / HDLC cancel transfer register (0x020030A) RXIEC: HDLC clear Rx and Sp INT enable(D1) / HDLC cancel transfer register (0x020030A) TXIEC: HDLC clear Tx INT enable (D0) / HDLC cancel transfer register (0x020030A) Writing "1" to a bit clears the corresponding enable bit in the HDLC transfer settings register.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES TXFTH[1:0]: HDLC transmit queue interrupt threshold (D[1:0]) / HDLC transmit queue threshold register (0x020031A) These bits specify the level triggering transmit queue interrupts: from 0 for completely empty to 3 for at least one slot free.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES RXADD[7:0]: HDLC receive address (D[7:0]) / HDLC receive address register (0x020030C) This register specifies the address for filtering incoming frames based on the byte immediately following the opening flag pattern. If the HDLC receive operation settings register (D7/0x020030E) specifies address comparison, the hardware rejects frames whose address fields do not match this value. Otherwise, it accepts them all.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES RXINTS[1:0]: HDLC receive interrupt setup (D[1:0]) / HDLC receive interrupt mode settings register (0x0200312) These bits offer a choice of three Rx INT interrupt configurations. (1) RXINTS = 00: Rx INT and Sp INT on first receive character Note that this mode of operation requires a receive queue interrupt threshold setting of zero to guarantee proper operation.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES RXD[7:0]: HDLC receive data (D[7:0]) / HDLC receive data register (0x0200316) This read-only register is for reading bytes from the receive queue, updating both the queue and the status registers. (For further details on the latter, see the descriptions of the status registers.) The HDLC interface receives the LSB (bit 0) first.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES ABORT: HDLC Abort detected (D7) / HDLC E/S INT receive status register (0x020032C) TXUE: HDLC Tx underrun/EOM detected (D5) / HDLC E/S INT receive status register (0x020032C) Hunt: HDLC Hunt detected (D1) / HDLC E/S INT receive status register (0x020032C) IDLED: HDLC Idle detected (D0) / HDLC E/S INT receive status register (0x020032C) These bits give the status for E/S INT interrupt triggers.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES RXOVR: HDLC Rx overrun detected (D7) / HDLC Sp INT receive status register (0x020032E) EOF: HDLC end of frame detected (D6) / HDLC Sp INT receive status register (0x020032E) SHFD: HDLC short frame detected (D0) / HDLC Sp INT receive status register (0x020032E) These bits give the status for Sp INT interrupt triggers. Note that Sp INT interrupt requests lock the receive queue and that reading the receive data register updates this register.
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES Important Notes on Debugging ICD33 debugging mode supports the use of the ICD33MODE signal from the CPU core to hold certain communications block input signals at their current levels and thus simulate suspension of communications.
S1C33210 FUNCTION PART IV ANALOG BLOCK
IV ANALOG BLOCK: INTRODUCTION IV-1 INTRODUCTION The analog block consists of a 10-bit A/D converter with 4 input channels. C33 DMA Block C33 Internal Memory Block C33_DMA (IDMA, HSDMA) CORE_PAD Internal RAM (Area 0) C33_CORE (CPU, BCU, ITC, CLG, DBG) Pads C33_SBUS C33_ADC C33_PERI (A/D converter) (Prescaler, 8-bit timer, 16-bit timer, Clock timer, Serial interface, Mobile access interface, Ports) C33 Analog Block PERI_PAD C33 Core Block Pads C33 Peripheral Block Figure 1.
IV ANALOG BLOCK: INTRODUCTION THIS PAGE IS BLANK.
IV ANALOG BLOCK: A/D CONVERTER IV-2 A/D CONVERTER Features and Structure of A/D Converter The Analog Block contains an A/D converter with the following features: • Conversion method: Successive comparison • Resolution: 10 bits • Input channels: Maximum of 4 • Conversion time: Maximum of 10 µs (when a 2-MHz input clock is selected) • Conversion range: Between VSS and AVDD • Two conversion modes can be selected: Normal mode: Conversion is completed in one operation.
IV ANALOG BLOCK: A/D CONVERTER I/O Pins of A/D Converter Table 2.1 shows the pins used by the A/D converter. Table 2.
IV ANALOG BLOCK: A/D CONVERTER Setting A/D Converter When the A/D converter is used, the following settings must be made before an A/D conversion can be performed: 1. Setting analog input pins 2. Setting the input clock 3. Selecting the analog-conversion start and end channels 4. Setting the A/D conversion mode 5. Selecting a trigger 6. Setting the sampling time 7. Setting interrupt/IDMA/HSDMA The following describes how to set each item.
IV ANALOG BLOCK: A/D CONVERTER Table 2.3 Relationship between CS/CE and Input Channel CS2/CE2 CS1/CE1 CS0/CE0 Channel selected 0 0 0 0 1 1 0 0 1 0 1 0 AD3 AD2 AD1 AD0 The CS setting must be less than or equal to the CE setting.
IV ANALOG BLOCK: A/D CONVERTER Control and Operation of A/D Conversion Figure 2.2 shows the operation of the A/D converter.
IV ANALOG BLOCK: A/D CONVERTER When a trigger is input, the A/D converter samples and A/D-converts the analog input signal, beginning with the conversion start channel selected by CS[2:0].
IV ANALOG BLOCK: A/D CONVERTER A/D Converter Interrupt and DMA Upon completion of A/D conversion in each channel, the A/D converter generates an interrupt and invokes the DMA if necessary.
IV ANALOG BLOCK: A/D CONVERTER Trap vector The A/D converter's interrupt trap-vector default address is set to 0x0C00100. The base address of the trap table can be changed using the TTBR register (0x48134 to 0x48137).
IV ANALOG BLOCK: A/D CONVERTER I/O Memory of A/D Converter Table 2.6 shows the control bits of the A/D converter. For details on the I/O memory of the prescaler used to set clocks, refer to "Prescaler". For details on the I/O memory of the programmable timers used for a trigger, refer to "8-Bit Programmable Timers" or "16-Bit Programmable Timers". Table 2.
IV ANALOG BLOCK: A/D CONVERTER Register name Address Bit Serial I/F Ch.1, 004026A A/D interrupt (B) priority register D7 D6 D5 D4 D3 D2 D1 D0 Setting Init. – PAD2 PAD1 PAD0 – PSIO12 PSIO11 PSIO10 Name reserved A/D converter interrupt level Function – 0 to 7 – 0 when being read. R/W reserved Serial interface Ch.1 interrupt level – 0 to 7 – X X X – X X X – 0 0 0 0 0 0 – 0 when being read. R/W R/W R/W R/W R/W R/W – X X X X X X – 0 when being read.
IV ANALOG BLOCK: A/D CONVERTER ADD9–ADD0: A/D converted data (D[1:0]) / A/D conversion result (high-order) register (0x40241) (D[7:0]) / A/D conversion result (low-order) register (0x40240) Stores the results of A/D conversion. The LSB is stored in ADD0, and the MSB is stored in ADD9. ADD0 and ADD1 are mapped to bits D0 and D1 at the address 0x40241, but bits D2 through D7 are always 0 when read. This is a read-only register, so writing to this register is ignored.
IV ANALOG BLOCK: A/D CONVERTER ADF: Conversion-complete flag (D3) / A/D enable register (0x40244) Indicates that A/D conversion has been completed. Read "1": Conversion completed Read "0": Being converted or standing by Write: Invalid This flag is set to "1" when A/D conversion is completed, and the converted data is stored in the data register and is reset to "0" when the converted data is read out.
IV ANALOG BLOCK: A/D CONVERTER ST1–ST0: Sampling-time setup (D[1:0]) / A/D sampling register (0x40245) Sets the analog input sampling time. Table 2.8 Sampling Time ST1 ST0 Sampling Time 1 1 1 0 0 1 0 0 The A/D converter input 9-clock period 7-clock period 5-clock period 3-clock period clock is used for counting. At initial reset, ST is set to "11" (9-clock period). To maintain the conversion accuracy, use ST as set by default (9-clock period).
IV ANALOG BLOCK: A/D CONVERTER The interrupt factor flag is set to "1" whenever interrupt generation conditions are met, regardless of how the interrupt enable and interrupt priority registers are set.
IV ANALOG BLOCK: A/D CONVERTER Programming Notes (1) Before setting the conversion mode, start/end channels, etc. for the A/D converter, be sure to disable the A/D converter (ADE (D2) / A/D enable register (0x40244) = "0"). A change in settings while the A/D converter is enabled could cause it to operate erratically. (2) The A/D converter operates only when the prescaler is operating. When the A/D converter registers are set up, the prescaler must be operating.
IV ANALOG BLOCK: A/D CONVERTER THIS PAGE IS BLANK.
S1C33210 FUNCTION PART V DMA BLOCK
V DMA BLOCK: INTRODUCTION V-1 INTRODUCTION The DMA block is configured with two types of DMA controllers: HSDMA (High-Speed DMA) that has on-chip registers for controlling DMA command information and IDMA (Intelligent DMA) that uses a memory area for storing DMA command information.
V DMA BLOCK: INTRODUCTION THIS PAGE IS BLANK.
V DMA BLOCK: HSDMA (High-Speed DMA) V-2 HSDMA (High-Speed DMA) Functional Outline of HSDMA The DMA Block contains four channels of HSDMA (High-Speed DMA) circuits that support dual-address transfer and single-address transfer methods. Since the control registers required for the DMA function are built into the chip, DMA requests for data transfer can be responded to instantaneously. Note: Only two DMA channels support external requests.
V DMA BLOCK: HSDMA (High-Speed DMA) I/O Pins of HSDMA Table 2.1 lists the I/O pins used for HSDMA. Table 2.
V DMA BLOCK: HSDMA (High-Speed DMA) Programming Control Information The HSDMA operates according to the control information set in the registers. Note that some control bits change their functions according to the address mode. The following explains how to set the contents of control information. Before using HSDMA, make each the settings described below. Setting the Registers in Dual-Address Mode Make sure that the HSDMA channel is disabled (HSx_EN = "0") before setting the control information.
V DMA BLOCK: HSDMA (High-Speed DMA) Block length When using block transfer mode (DxMOD = "10"), the data block length (in units of DATSIZEx) should be set using the BLKLENx[7:0] bits. BLKLEN0[7:0]: Ch. 0 block length (D[7:0]) / HSDMA Ch. 0 transfer counter register (0x48220) BLKLEN1[7:0]: Ch. 1 block length (D[7:0]) / HSDMA Ch. 1 transfer counter register (0x48230) BLKLEN2[7:0]: Ch. 2 block length (D[7:0]) / HSDMA Ch. 2 transfer counter register (0x48240) BLKLEN3[7:0]: Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) D0ADRL[15:0]: D1ADRL[15:0]: D2ADRL[15:0]: D3ADRL[15:0]: D0ADRH[11:0]: D1ADRH[11:0]: D2ADRH[11:0]: D3ADRH[11:0]: Ch. 0 destination address [15:0] (D[F:0]) / Ch. 0 low-order destination address set-up register (0x48228) Ch. 1 destination address [15:0] (D[F:0]) / Ch. 1 low-order destination address set-up register (0x48238) Ch. 2 destination address [15:0] (D[F:0]) / Ch. 2 low-order destination address set-up register (0x48248) Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) Setting the Registers in Single-Address Mode Make sure that the HSDMA channel is disabled (HSx_EN = "0") before seffing the control information. Address mode The address mode select bit DUALMx should be set to "0" (single-address mode). This bit is set to "0" at initial reset. Transfer mode A transfer mode should be set using the DxMOD[1:0] bits.
V DMA BLOCK: HSDMA (High-Speed DMA) Address increment/decrement control The memory addresses can be incremented or decremented when one data transfer is completed. SxIN[1:0] is used to set this function. S0IN[1:0]: Ch. 0 memory address control (D[D:C]) / Ch. 0 high-order source address set-up register (0x48226) S1IN[1:0]: Ch. 1 memory address control (D[D:C]) / Ch. 1 high-order source address set-up register (0x48236) S2IN[1:0]: Ch. 2 memory address control (D[D:C]) / Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) Trigger Factor A HSDMA tigger factor can be selected from among 13 types using the HSDMA trigger set-up register for each channel. This function is supported by the interrupt controller. HSD0S[3:0]: Ch. 0 trigger set-up (D[3:0]) / HSDMA Ch. 0/1 trigger set-up register (0x40298) HSD1S[3:0]: Ch. 1 trigger set-up (D[7:4]) / HSDMA Ch. 0/1 trigger set-up register (0x40298) HSD2S[3:0]: Ch. 2 trigger set-up (D[3:0]) / HSDMA Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) Operation of HSDMA An HSDMA channel starts data transfer by the selected trigger factor. Make sure that transfer conditions and a trigger factor are set and the HSDMA channel is enabled before starting a DMA transfer. Operation in Dual-Address Mode In dual-address mode, both the source and destination addresses are accessed according to the bus condition set by the BCU. HSDMA has three transfer modes, in each of which data transfer operates differently.
V DMA BLOCK: HSDMA (High-Speed DMA) Successive transfer mode The channel for which DxMOD in control information is set to "01" operates in successive transfer mode. In this mode, a data transfer is performed by one trigger a number of times as set by the transfer counter. The transfer counter is decremented to "0" by one transfer executed. The operation of HSDMA in successive transfer mode is shown by the flow chart in Figure 2.4.
V DMA BLOCK: HSDMA (High-Speed DMA) Block transfer mode The channel for which DxMOD in control information is set to "10" operates in block transfer mode. In this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by BLKLENx. If a block transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. The operation of HSDMA in block transfer mode is shown by the flow chart in Figure 2.
V DMA BLOCK: HSDMA (High-Speed DMA) Operation in Single-Address Mode The operation of each transfer mode is almost the same as that of dual-address mode (see the previous section). However, data read/write operation is performed simultaneously in single-address mode. The following explains the data transfer operation different from dual-address mode.
V DMA BLOCK: HSDMA (High-Speed DMA) Timing Chart Dual-address mode (1) SRAM Example: When 2 (RD)/1 (WR) wait cycles are inserted Read cycle Write cycle source address destination address BCLK A[23:0] #CE(src) ;;; ;;; #CE(dst) #RD #WRH/#WRL #DMAEND Figure 2.
V DMA BLOCK: HSDMA (High-Speed DMA) Single-address mode (1) SRAM Example: When 2 (RD)/1 (WR) wait cycles are inserted BCLK ;;; ;;; addr A[23:0] #CExx #RD #WRH/#WRL #DMAACK #DMAEND Figure 2.
V DMA BLOCK: HSDMA (High-Speed DMA) Interrupt Function of HSDMA The DMA controller can generate an interrupt when the transfer counter in each HSDMA channel reaches 0. Furthermore, channels 0 and 1 can invoke IDMA using their interrupt factor. Control registers of the interrupt controller Table 2.3 shows the control registers of the interrupt controller that are provided for each channel. Table 2.3 Control Registers of Interrupt Controller Channel Ch. Ch. Ch. Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) Intelligent DMA Intelligent DMA (IDMA) can be invoked by the end-of-transfer interrupt factor of channels 0 and 1 of HSDMA. The following shows the IDMA channels set in HSDMA: IDMA channel Channel 0 end-of-transfer interrupt: 0x05 Channel 1 end-of-transfer interrupt: 0x06 Before IDMA can be invoked, the corresponding bits of the IDMA request and IDMA enable registers must be set to "1". Settings of transfer conditions on the IDMA side are also required. Table 2.
V DMA BLOCK: HSDMA (High-Speed DMA) I/O Memory of HSDMA Table 2.5 shows the control bits of HSDMA. Table 2.5 Control Bits of HSDMA Register name Address Bit Setting Init. High-speed 0040263 DMA Ch.0/1 (B) interrupt priority register D7 D6 D5 D4 D3 D2 D1 D0 – PHSD1L2 PHSD1L1 PHSD1L0 – PHSD0L2 PHSD0L1 PHSD0L0 reserved High-speed DMA Ch.1 interrupt level – 0 to 7 – 0 when being read. R/W reserved High-speed DMA Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) Register name Address Bit Name High-speed DMA Ch.0/1 trigger set-up register D7 D6 D5 D4 HSD1S3 HSD1S2 HSD1S1 HSD1S0 High-speed DMA Ch.1 trigger set-up D3 D2 D1 D0 HSD0S3 HSD0S2 HSD0S1 HSD0S0 High-speed DMA Ch.0 trigger set-up D7 D6 D5 D4 HSD3S3 HSD3S2 HSD3S1 HSD3S0 High-speed DMA Ch.3 trigger set-up D3 D2 D1 D0 HSD2S3 HSD2S2 HSD2S1 HSD2S0 High-speed DMA Ch.2 trigger set-up High-speed DMA Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) Register name Address Bit P1 function select register D7 D6 – CFP16 reserved P16 function selection 1 D5 CFP15 P15 function selection 1 D4 CFP14 P14 function selection D3 CFP13 P13 function selection D2 CFP12 P12 function selection D1 CFP11 P11 function selection D0 CFP10 P10 function selection D7 D6 D5 D4 D3 D2 D1 D0 – IOC16 IOC15 IOC14 IOC13 IOC12 IOC11 IOC10 reserved P16 I/O control P15 I/O control P14 I/O control P13 I/O control P12 I/O cont
V DMA BLOCK: HSDMA (High-Speed DMA) Register name Address Bit Name High-speed 0048222 DMA Ch.0 (HW) control register DF DE DUALM0 D0DIR DD–8 D7 D6 D5 D4 D3 D2 D1 D0 – TC0_H7 TC0_H6 TC0_H5 TC0_H4 TC0_H3 TC0_H2 TC0_H1 TC0_H0 Note: D) Dual address mode S) Single address mode High-speed 0048224 DMA Ch.0 (HW) low-order source address set-up register Note: D) Dual address mode S) Single address mode High-speed 0048226 DMA Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) Register name Address Bit Name High-speed 004822A DMA Ch.0 (HW) high-order destination address set-up register DF DE D0MOD1 D0MOD0 Ch.0 transfer mode DD DC D0IN1 D0IN0 D) Ch.0 destination address control S) Invalid DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 D0ADRH11 D) Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) Register name Address Bit High-speed 0048234 DMA Ch.1 (HW) low-order source address set-up register DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 S1ADRL15 D) Ch.1 source address[15:0] S1ADRL14 S) Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) Register name Address Bit Name High-speed 004823A DMA Ch.1 (HW) high-order destination address set-up register DF DE D1MOD1 D1MOD0 Ch.1 transfer mode DD DC D1IN1 D1IN0 D) Ch.1 destination address control S) Invalid DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 D1ADRH11 D) Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) Register name Address Bit High-speed 0048244 DMA Ch.2 (HW) low-order source address set-up register DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 S2ADRL15 D) Ch.2 source address[15:0] S2ADRL14 S) Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) Register name Address Bit Name High-speed 004824A DMA Ch.2 (HW) high-order destination address set-up register DF DE D2MOD1 D2MOD0 Ch.2 transfer mode DD DC D2IN1 D2IN0 D) Ch.2 destination address control S) Invalid DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 D2ADRH11 D) Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) Register name Address Bit High-speed 0048254 DMA Ch.3 (HW) low-order source address set-up register DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 S3ADRL15 D) Ch.3 source address[15:0] S3ADRL14 S) Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) Register name Address Bit Name High-speed 004825A DMA Ch.3 (HW) high-order destination address set-up register DF DE D3MOD1 D3MOD0 Ch.3 transfer mode DD DC D3IN1 D3IN0 D) Ch.3 destination address control S) Invalid DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 D3ADRH11 D) Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) IOC16–IOC15: P1[6:5] port I/O control (D[6:5]) / P1 I/O control register (0x402D6) Direct the I/O port for input or output. Write "1": Output mode Write "0": Input mode Read: Valid To use the #DMAEND0 pin (channel 0), direct the pin for output by writing "1" to IOC15; to use the #DMAEND1 pin (channel 1), direct the pin for output by writing "1" to IOC16.
V DMA BLOCK: HSDMA (High-Speed DMA) HSD0S3–HSD0S0: Ch. HSD1S3–HSD1S0: Ch. HSD2S3–HSD2S0: Ch. HSD3S3–HSD3S0: Ch. 0 1 2 3 trigger set-up trigger set-up trigger set-up trigger set-up (D[3:0]) / HSDMA Ch. (D[7:4]) / HSDMA Ch. (D[3:0]) / HSDMA Ch. (D[7:4]) / HSDMA Ch. 0/1 trigger set-up 0/1 trigger set-up 2/3 trigger set-up 2/3 trigger set-up register (0x40298) register (0x40298) register (0x40299) register (0x40299) Select a trigger factor for each HSDMA channel. Table 2.
V DMA BLOCK: HSDMA (High-Speed DMA) HS0_EN: Ch. HS1_EN: Ch. HS2_EN: Ch. HS3_EN: Ch. 0 1 2 3 enable enable enable enable (D0) / HSDMA Ch. (D1) / HSDMA Ch. (D2) / HSDMA Ch. (D3) / HSDMA Ch. 0 1 2 3 enable enable enable enable register (0x4822C) register (0x4823C) register (0x4824C) register (0x4825C) Enable a DMA transfer. Write "1": Enabled Write "0": Disabled Read: Valid DMA transfer is enabled by writing "1" to this bit.
V DMA BLOCK: HSDMA (High-Speed DMA) D0MOD1–D0MOD0: Ch. 0 transfer mode (D[F:E]) / Ch. 0 high-order destination address set-up register (0x4822A) D1MOD1–D1MOD0: Ch. 1 transfer mode (D[F:E]) / Ch. 1 high-order destination address set-up register (0x4823A) D2MOD1–D2MOD0: Ch. 2 transfer mode (D[F:E]) / Ch. 2 high-order destination address set-up register (0x4824A) D3MOD1–D3MOD0: Ch. 3 transfer mode (D[F:E]) / Ch. 3 high-order destination address set-up register (0x4825A) Select a transfer mode. Table 2.
V DMA BLOCK: HSDMA (High-Speed DMA) D0IN1–D0IN0: Ch. 0 destination address control (D[D:C]) / Ch. 0 high-order destination address set-up register (0x4822A) D1IN1–D1IN0: Ch. 1 destination address control (D[D:C]) / Ch. 1 high-order destination address set-up register (0x4823A) D2IN1–D2IN0: Ch. 2 destination address control (D[D:C]) / Ch. 2 high-order destination address set-up register (0x4824A) D3IN1–D3IN0: Ch. 3 destination address control (D[D:C]) / Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) S0ADRL15–S0ADRL0: Ch. 0 source (D[F:0]) / Ch. S0ADRH11–S0ADRH0: Ch. 0 source (D[B:0]) / Ch. S1ADRL15–S1ADRL0: Ch. 1 source (D[F:0]) / Ch. S1ADRH11–S1ADRH0: Ch. 1 source (D[B:0]) / Ch. S2ADRL15–S2ADRL0: Ch. 2 source (D[F:0]) / Ch. S2ADRH11–S2ADRH0: Ch. 2 source (D[B:0]) / Ch. S3ADRL15–S3ADRL0: Ch. 3 source (D[F:0]) / Ch. S3ADRH11–S3ADRH0: Ch. 3 source (D[B:0]) / Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) EHDM0: Ch. EHDM1: Ch. EHDM2: Ch. EHDM3: Ch. 0 1 2 3 interrupt interrupt interrupt interrupt enable enable enable enable (D0) / DMA interrupt enable register (0x40271) (D1) / DMA interrupt enable register (0x40271) (D2) / DMA interrupt enable register (0x40271) (D3) / DMA interrupt enable register (0x40271) Enable or disable interrupt generation to the CPU.
V DMA BLOCK: HSDMA (High-Speed DMA) RHDM0: Ch.0 IDMA request (D4) / Port input 0–3, HSDMA, 16-bit timer 0 IDMA request register (0x40290) RHDM1: Ch.1 IDMA request (D5) / Port input 0–3, HSDMA, 16-bit timer 0 IDMA request register (0x40290) Specify whether IDMA need to be invoked when an interrupt factor occurs.
V DMA BLOCK: HSDMA (High-Speed DMA) Programming Notes (1) When setting the transfer conditions, always make sure the DMA controller is inactive (HSx_EN = "0"). (2) After an initial reset, the interrupt factor flag (FHDMx) becomes indeterminate. Always be sure to reset the flag to prevent interrupts or IDMA requests from being generated inadvertently.
V DMA BLOCK: IDMA (Intelligent DMA) V-3 IDMA (Intelligent DMA) Functional Outline of IDMA The DMA Block contains an intelligent DMA (IDMA), a function that allows control information to be programmed in RAM. Up to 128 channels can be programmed, including 31 channels that are invoked by an interrupt factor that occurs in some internal peripheral circuit.
V DMA BLOCK: IDMA (Intelligent DMA) The contents of control information (3 words) in each channel are shown in the table below. Table 3.
V DMA BLOCK: IDMA (Intelligent DMA) BLKLEN[7:0]: Block size/transfer counter (D[7:0]/1st Word) In block transfer mode, set the size of a block that is transferred in one operation (in units of DATSIZ). In single transfer and successive transfer modes, set an 8-bit low-order value for the transfer count here. Note: The transfer count and block size thus set are decremented according to the transfers performed.
V DMA BLOCK: IDMA (Intelligent DMA) DSINC[1:0]: Destination address control (D[29:28]/3rd Word) Set the destination address update format. If the format is set for "address fixed" (00), the destination address is not changed by the performance of a data transfer operation. Even when transferring multiple data, the transfer data is always written to the same address.
V DMA BLOCK: IDMA (Intelligent DMA) IDMA Invocation The triggers by which IDMA is invoked have the following three causes: 1. Interrupt factor in an internal peripheral circuit 2. Trigger in the software application 3. Link setting Enabling/disabling DMA transfer The IDMA controller is enabled by writing "1" to the IDMA enable bit IDMAEN (D0) / IDMA enable register (0x48205), and is ready to accept the triggers described above.
V DMA BLOCK: IDMA (Intelligent DMA) These interrupt factors are used in common for interrupt requests and IDMA invocation requests. To invoke IDMA upon the occurrence of an interrupt factor, set the corresponding bits of the IDMA request and IDMA enable registers shown in the table by writing "1". Then when an interrupt factor occurs, an interrupt request to the CPU is kept pending and the corresponding IDMA channel is invoked.
V DMA BLOCK: IDMA (Intelligent DMA) IDMA invocation request during a DMA transfer An IDMA invocation request to another channel that is generated during a DMA transfer is kept pending until the DMA transfer that was being executed at the time is completed. Since an invocation request is not cleared, new requests will be accepted when the DMA transfer under execution is completed.
V DMA BLOCK: IDMA (Intelligent DMA) Operation of IDMA IDMA has three transfer modes, in each of which data transfer operates differently. Furthermore, an interrupt factor is processed differently depending on the type of trigger. The following describes the operation of IDMA in each transfer mode and how an interrupt factor is processed for each type of trigger. Single transfer mode The channels for which DMOD in control information is set to "00" operate in single transfer mode.
V DMA BLOCK: IDMA (Intelligent DMA) Successive transfer mode The channels for which DMOD in control information is set to "01" operate in successive transfer mode. In this mode, a data transfer is performed by one trigger a number of times as set by the transfer counter. The transfer counter is decremented to "0" by one transfer executed. The operation of IDMA in successive transfer mode is shown by the flow chart in Figure 3.2.
V DMA BLOCK: IDMA (Intelligent DMA) Block transfer mode The channels for which DMOD in control information is set to "10" operate in block transfer mode. In this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by BLKLEN. If a block transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. The operation of IDMA in block transfer mode is shown by the flow chart in Figure 3.3.
V DMA BLOCK: IDMA (Intelligent DMA) Processing of interrupt factors by type of trigger • When invoked by an interrupt factor The interrupt factor flag by which IDMA has been invoked remains set even during a DMA transfer. If the transfer counter is decremented to 0 and DINTEN = "1" (interrupt enabled) when one DMA transfer is completed, the interrupt factor that has invoked IDMA is not reset and an interrupt request is generated. At the same time, the IDMA request register is cleared to "0".
V DMA BLOCK: IDMA (Intelligent DMA) Linking If the IDMA channel number to be executed next is set in the IDMA link field "LNKCHN" of control information and LNKEN is set to "1" (link enabled), DMA successive transfer in that IDMA channel can be performed. An example of link setting is shown in Figure 3.6. Trigger After transfer Ch.3 Ch.5 Ch.
V DMA BLOCK: IDMA (Intelligent DMA) Interrupt Function of Intelligent DMA IDMA can generate an interrupt that causes invocation of IDMA and an interrupt for the completion of IDMA transfer itself. Interrupt when invoked by an interrupt factor If the corresponding bits of the IDMA request and interrupt enable registers are left set (= "1"), assertion of an interrupt request is kept pending even when the enabled interrupt factor has occurred and the IDMA channel assigned to that interrupt factor is invoked.
V DMA BLOCK: IDMA (Intelligent DMA) Trap vector The trap vector address for an interrupt upon completion of IDMA transfer by default is set to 0x0C00068. The trap table base address can be changed using the TTBR registers (0x48134 to 0x48137). I/O Memory of Intelligent DMA Table 3.3 shows the control bits of IDMA. Table 3.
V DMA BLOCK: IDMA (Intelligent DMA) DBASEL[15:0]: IDMA base address [15:0] (D[F:0]) / IDMA base address low-order register (0x48200) DDBASEH[11:0]: IDMA base address [27:16] (D[B:0]) / IDMA base address high-order register (0x48202) Specify the starting address of the control information to be placed in RAM. Use DBASEL to set the 16 low-order bits of the address and DBASEH to set the 12 high-order bits. The address to be set in these registers must always be a word (32-bit) boundary address.
V DMA BLOCK: IDMA (Intelligent DMA) FIDMA: IDMA interrupt factor flag (D2) / DMA interrupt factor flag register (0x40281) Indicate the occurrence status of an IDMA interrupt request.
V DMA BLOCK: IDMA (Intelligent DMA) Programming Notes (1) Before setting the IDMA base address, be sure to disable DMA transfers (IDMAEN = "0"). Writing to the IDMA base address register is ignored when the DMA transfer is enabled (IDMAEN = "1"). Also, when the register is read during a DMA transfer, the data is indeterminate. When setting or rewriting control information for each channel, make sure that DMA transfers will not occur in any channel.
V DMA BLOCK: IDMA (Intelligent DMA) THIS PAGE IS BLANK.
S1C33210 FUNCTION PART Appendix I/O MAP
APPENDIX: I/O MAP Register name Address 8-bit timer 4/5 clock select register 0040140 (B) 8-bit timer 4/5 clock control register 0040145 (B) Bit Name D7–2 – D1 P8TPCK5 D0 P8TPCK4 D7 D6 D5 D4 D3 D2 D1 D0 P8TON5 P8TS52 P8TS51 P8TS50 P8TON4 P8TS42 P8TS41 P8TS40 Function reserved 8-bit timer 5 clock selection 8-bit timer 4 clock selection 8-bit timer 5 clock control 8-bit timer 5 clock division ratio selection 8-bit timer 4 clock control 8-bit timer 4 clock division ratio selection 8-bit timer cl
APPENDIX: I/O MAP Register name Address Bit Name Function 16-bit timer 3 clock control register 004014A D7–4 – (B) D3 P16TON3 D2 P16TS32 D1 P16TS31 D0 P16TS30 reserved 16-bit timer 3 clock control 16-bit timer 3 clock division ratio selection 16-bit timer 4 clock control register 004014B D7–4 – (B) D3 P16TON4 D2 P16TS42 D1 P16TS41 D0 P16TS40 reserved 16-bit timer 4 clock control 16-bit timer 4 clock division ratio selection 16-bit timer 5 clock control register 004014C D7–4 – (B) D3 P16TON5 D2 P
APPENDIX: I/O MAP Register name Address Bit Name 8-bit timer 2/3 clock control register D7 D6 D5 D4 P8TON3 P8TS32 P8TS31 P8TS30 004014E (B) D3 D2 D1 D0 P8TON2 P8TS22 P8TS21 P8TS20 A/D clock 004014F control register (B) D7–4 D3 D2 D1 D0 Clock timer Run/Stop register D7–2 – D1 TCRST D0 TCRUN 0040151 (B) Clock timer 0040152 interrupt (B) control register Clock timer 0040153 divider register (B) Clock timer second register 0040154 (B) – PSONAD PSAD2 PSAD1 PSAD0 Function 8-bit timer 3 clock c
APPENDIX: I/O MAP Register name Address Bit Clock timer 0040155 minute register (B) D7–6 D5 D4 D3 D2 D1 D0 – TCHD5 TCHD4 TCHD3 TCHD2 TCHD1 TCHD0 reserved Clock timer minute counter data TCHD5 = MSB TCHD0 = LSB Clock timer hour register D7–5 D4 D3 D2 D1 D0 – TCDD4 TCDD3 TCDD2 TCDD1 TCDD0 Clock timer 0040157 day (low-order) (B) register D7 D6 D5 D4 D3 D2 D1 D0 Clock timer day (highorder) register 0040158 (B) Clock timer minute comparison register 0040159 (B) Clock timer hour comparison registe
APPENDIX: I/O MAP Register name Address Bit 8-bit timer 0 0040160 control register (B) D7–3 D2 D1 D0 Name Function – PTOUT0 PSET0 PTRUN0 reserved 8-bit timer 0 clock output control 8-bit timer 0 preset 8-bit timer 0 Run/Stop control Setting – 1 On 1 Preset 1 Run 0 Off 0 Invalid 0 Stop Init. R/W Remarks – 0 – 0 – 0 when being read. R/W W 0 when being read.
APPENDIX: I/O MAP Register name Address Bit Name Function 8-bit timer 3 004016C D7–3 – control register (B) D2 PTOUT3 D1 PSET3 D0 PTRUN3 reserved 8-bit timer 3 clock output control 8-bit timer 3 preset 8-bit timer 3 Run/Stop control 8-bit timer 3 reload data register 004016D (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD37 RLD36 RLD35 RLD34 RLD33 RLD32 RLD31 RLD30 8-bit timer 3 reload data RLD37 = MSB RLD30 = LSB 8-bit timer 3 counter data register 004016E (B) D7 D6 D5 D4 D3 D2 D1 D0 PTD37 PTD36 PTD35 PTD34
APPENDIX: I/O MAP Register name Address Bit Name Function Setting Init. R/W Remarks Watchdog 0040170 timer write(B) protect register D7 WRWD D6–0 – EWD write protection – 1 Write enabled 0 Write-protect – 0 – R/W – 0 when being read. Watchdog timer enable register D7–2 – D1 EWD D0 – – Watchdog timer enable – – 1 NMI enabled 0 NMI disabled – – 0 – – 0 when being read. R/W – 0 when being read.
APPENDIX: I/O MAP Register name Address Bit Name Power control register D7 D6 CLKDT1 CLKDT0 System clock division ratio selection D5 D4–3 D2 D1 D0 PSCON – CLKCHG SOSC3 SOSC1 Prescaler On/Off control reserved 1 OSC3 CPU operating clock switch High-speed (OSC3) oscillation On/Off 1 On Low-speed (OSC1) oscillation On/Off 1 On 0040180 (B) Function Setting CLKDT[1:0] 1 1 1 0 0 1 0 0 1 On R/W 1 0 1 1 1 R/W – Writing 1 not allowed. R/W R/W R/W – 0 0 – R/W – 0 1 0 0 – 0 when being read.
APPENDIX: I/O MAP Register name Address Bit Serial I/F Ch.0 transmit data register 00401E0 (B) D7 D6 D5 D4 D3 D2 D1 D0 TXD07 TXD06 TXD05 TXD04 TXD03 TXD02 TXD01 TXD00 Name Serial I/F Ch.0 transmit data TXD07(06) = MSB TXD00 = LSB Function 0x0 to 0xFF(0x7F) X X X X X X X X Serial I/F Ch.0 receive data register 00401E1 (B) D7 D6 D5 D4 D3 D2 D1 D0 RXD07 RXD06 RXD05 RXD04 RXD03 RXD02 RXD01 RXD00 Serial I/F Ch.
APPENDIX: I/O MAP Register name Address Bit Serial I/F Ch.1 transmit data register 00401E5 (B) D7 D6 D5 D4 D3 D2 D1 D0 TXD17 TXD16 TXD15 TXD14 TXD13 TXD12 TXD11 TXD10 Name Serial I/F Ch.1 transmit data TXD17(16) = MSB TXD10 = LSB Function 0x0 to 0xFF(0x7F) X X X X X X X X Serial I/F Ch.1 receive data register 00401E6 (B) D7 D6 D5 D4 D3 D2 D1 D0 RXD17 RXD16 RXD15 RXD14 RXD13 RXD12 RXD11 RXD10 Serial I/F Ch.
APPENDIX: I/O MAP Register name Address Bit Serial I/F Ch.2 00401F3 control register (B) D7 D6 D5 D4 D3 D2 D1 D0 TXEN2 RXEN2 EPR2 PMD2 STPB2 SSCK2 SMD21 SMD20 Name Ch.2 transmit enable Ch.2 receive enable Ch.2 parity enable Ch.2 parity mode selection Ch.2 stop bit selection Ch.2 input clock selection Ch.2 transfer mode selection Function – DIVMD2 IRTL2 IRRL2 IRMD21 IRMD20 reserved Ch.2 async. clock division ratio Ch.2 IrDA I/F output logic inversion Ch.2 IrDA I/F input logic inversion Ch.
APPENDIX: I/O MAP Register name Address Bit A/D conversion 0040240 result (low(B) order) register D7 D6 D5 D4 D3 D2 D1 D0 Name ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 Function 0 0 0 0 0 0 0 0 R – 0x0 to 0x3FF (high-order 2 bits) – 0 0 – R – – 0 0 0 D7–2 – D1 ADD9 D0 ADD8 – A/D converted data (high-order 2 bits) ADD9 = MSB A/D trigger register D7–6 D5 D4 D3 – MS TS1 TS0 – A/D conversion mode selection A/D conversion trigger selection D2 D1 D0 CH2 CH1 CH0 A/D conversion channel status D
APPENDIX: I/O MAP Register name Address Bit Port input 0/1 0040260 interrupt (B) priority register D7 D6 D5 D4 D3 D2 D1 D0 – PP1L2 PP1L1 PP1L0 – PP0L2 PP0L1 PP0L0 reserved Port input 1 interrupt level – 0 to 7 reserved Port input 0 interrupt level – 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 – PP3L2 PP3L1 PP3L0 – PP2L2 PP2L1 PP2L0 reserved Port input 3 interrupt level – 0 to 7 reserved Port input 2 interrupt level – 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 – PK1L2 PK1L1 PK1L0 – PK0L2 PK0L1 PK0L0 reserved Key in
APPENDIX: I/O MAP Register name Address Bit 8-bit timer, 0040269 serial I/F Ch.0 (B) interrupt priority register D7 D6 D5 D4 D3 D2 D1 D0 – PSIO02 PSIO01 PSIO00 – P8TM2 P8TM1 P8TM0 reserved Serial interface Ch.0 interrupt level – 0 to 7 reserved 8-bit timer 0–3 interrupt level – 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 – PAD2 PAD1 PAD0 – PSIO12 PSIO11 PSIO10 reserved A/D converter interrupt level – 0 to 7 reserved Serial interface Ch.
APPENDIX: I/O MAP Register name Address Bit Key input, 0040270 port input 0–3 (B) interrupt enable register D7–6 D5 D4 D3 D2 D1 D0 – EK1 EK0 EP3 EP2 EP1 EP0 Name reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 Function DMA interrupt 0040271 enable register (B) D7–5 D4 D3 D2 D1 D0 – EIDMA EHDM3 EHDM2 EHDM1 EHDM0 reserved IDMA High-speed DMA Ch.3 High-speed DMA Ch.2 High-speed DMA Ch.1 High-speed DMA Ch.
APPENDIX: I/O MAP Register name Address Bit Key input, 0040280 port input 0–3 (B) interrupt factor flag register D7–6 D5 D4 D3 D2 D1 D0 – FK1 FK0 FP3 FP2 FP1 FP0 Name reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 Function DMA interrupt factor flag register 0040281 (B) D7–5 D4 D3 D2 D1 D0 – FIDMA FHDM3 FHDM2 FHDM1 FHDM0 reserved IDMA High-speed DMA Ch.3 High-speed DMA Ch.2 High-speed DMA Ch.1 High-speed DMA Ch.
APPENDIX: I/O MAP Register name Address Bit Name Port input 0–3, high-speed DMA Ch. 0/1, 16-bit timer 0 IDMA request register 0040290 (B) D7 D6 D5 D4 D3 D2 D1 D0 R16TC0 R16TU0 RHDM1 RHDM0 RP3 RP2 RP1 RP0 16-bit timer 0 comparison A 16-bit timer 0 comparison B High-speed DMA Ch.1 High-speed DMA Ch.
APPENDIX: I/O MAP Register name Address Bit Name High-speed DMA Ch.0/1 trigger set-up register D7 D6 D5 D4 HSD1S3 HSD1S2 HSD1S1 HSD1S0 High-speed DMA Ch.1 trigger set-up D3 D2 D1 D0 HSD0S3 HSD0S2 HSD0S1 HSD0S0 High-speed DMA Ch.0 trigger set-up D7 D6 D5 D4 HSD3S3 HSD3S2 HSD3S1 HSD3S0 High-speed DMA Ch.3 trigger set-up D3 D2 D1 D0 HSD2S3 HSD2S2 HSD2S1 HSD2S0 High-speed DMA Ch.2 trigger set-up High-speed DMA Ch.
APPENDIX: I/O MAP Register name Address Bit Name Function K5 function select register 00402C0 D7–4 – (B) D3 CP4 D2 CFK52 D1 CFK51 D0 CFK50 reserved CP4 K52 function selection K51 function selection K50 function selection K5 input port data register 00402C1 D7–5 – (B) D4 – D3 CP4D D2 K52D D1 K51D D0 K50D reserved – CP4 data K52 input port data K51 input port data K50 input port data K6 function select register 00402C3 (B) D7 D6 D5 D4 D3 D2 D1 D0 CP3 CP2 CP1 CP0 CFK63 CFK62 CFK61 CFK60 K6 input
APPENDIX: I/O MAP Register name Address Bit Interrupt factor 00402C5 FP function switching register D7 D6 T8CH5S0 SIO3TS0 8-bit timer 5 underflow SIO Ch.3 transmit buffer empty D5 D4 T8CH4S0 SIO3RS0 8-bit timer 4 underflow SIO Ch.3 receive buffer full D3 SIO2TS0 SIO Ch.2 transmit buffer empty D2 SIO3ES0 SIO Ch.3 receive error D1 SIO2RS0 SIO Ch.2 receive buffer full D0 SIO2ES0 SIO Ch.
APPENDIX: I/O MAP Register name Address Bit Name Function Key input interrupt (FPK0) input comparison register 00402CC D7–5 – (B) D4 SCPK04 D3 SCPK03 D2 SCPK02 D1 SCPK01 D0 SCPK00 reserved FPK04 input comparison FPK03 input comparison FPK02 input comparison FPK01 input comparison FPK00 input comparison Key input interrupt (FPK1) input comparison register 00402CD D7–4 – (B) D3 SCPK13 D2 SCPK12 D1 SCPK11 D0 SCPK10 reserved FPK13 input comparison FPK12 input comparison FPK11 input comparison FPK10 in
APPENDIX: I/O MAP Register name Address Bit P1 I/O control register 00402D6 (B) D7 D6 D5 D4 D3 D2 D1 D0 Port SIO function extension register 00402D7 D7–4 – D3 CFP322 reserved P32 function selection 2 1 – D2 CFP152 P15 function selection 2 1 – D1 CFP162 P16 function selection 2 1 – D0 CFP332 P33 function selection 2 1 – 00402D8 (B) D7 D6 D5 D4 D3 D2 D1 D0 CFP27 CFP26 CFP25 CFP24 CFP23 CFP22 CFP21 CFP20 P27 function selection P26 function selection P25 function selection P24 funct
APPENDIX: I/O MAP Register name Address Port function extension register 00402DF (B) Areas 18–15 0048120 set-up register (HW) Areas 14–13 0048122 set-up register (HW) Bit Name Function D7-6 D5 D4 D3 D2 D1 – CFEX5 CFEX4 CFEX3 CFEX2 CFEX1 reserved P05 port extended function P04 port extended function P31 port extended function P21 port extended function P10, P11, P13 port extended function D0 CFEX0 P12, P14 port extended function DF DE DD DC – A18SZ A18DF1 A18DF0 DB DA D9 D8 – A18WT2 A18WT1 A
APPENDIX: I/O MAP Register name Address Bit Areas 12–11 0048124 set-up register (HW) DF–7 D6 D5 D4 – A12SZ A12DF1 A12DF0 D3 D2 D1 D0 – A12WT2 A12WT1 A12WT0 Areas 10–9 0048126 set-up register (HW) Areas 8–7 0048128 set-up register (HW) B-APPENDIX-24 Name DF-B – DA A10BW1 D9 A10BW0 Function Setting Init. R/W Remarks reserved – Areas 12–11 device size selection 1 8 bits 0 16 bits Areas 12–11 A18DF[1:0] Number of cycles 1 1 3.5 output disable delay time 1 0 2.5 0 1 1.5 0 0 0.
APPENDIX: I/O MAP Register name Address Bit Name Areas 6–4 004812A DF–E – set-up register (HW) DD A6DF1 DC A6DF0 Function reserved Area 6 output disable delay time Setting – A6DF[1:0] Number of cycles 1 1 3.5 1 0 2.5 0 1 1.5 0 0 0.5 – A6WT[2:0] Wait cycles 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 – 1 8 bits 0 16 bits A5DF[1:0] Number of cycles 1 1 3.5 1 0 2.5 0 1 1.5 0 0 0.5 Init. R/W Remarks – 1 1 – 0 when being read. R/W – 1 1 1 – 0 when being read.
APPENDIX: I/O MAP Register name Address Bit Name Function DRAM timing 0048130 DF–C – reserved set-up register (HW) DB – reserved DA CEFUNC1 #CE pin function selection D9 CEFUNC0 Setting – – CFFUNC[1:0] #CE output 1 x #CE7/8..#CE17/18 #CE6..#CE17 0 1 #CE4..#CE10 0 0 1 Successive 0 Normal RPRC[1:0] Number of cycles 1 1 4 1 0 3 0 1 2 0 0 1 – CASC[1:0] Number of cycles 1 1 4 1 0 3 0 1 2 0 0 1 – RASC[1:0] Number of cycles 1 1 4 1 0 3 0 1 2 0 0 1 Init. R/W Remarks – – 0 0 – 0 when being read.
APPENDIX: I/O MAP Register name Address Bit G/A read signal 0048138 control register (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BCLK select register Name A18AS A16AS A14AS A12AS – A8AS A6AS A5AS A18RD A16RD A14RD A12RD – A8RD A6RD A5RD 004813A D7–4 – (B) D3 A1X1MD D2 – D1 BCLKSEL1 D0 BCLKSEL0 S1C33210 FUNCTION PART Function Area 18, 17 address strobe signal Area 16, 15 address strobe signal Area 14, 13 address strobe signal Area 12, 11 address strobe signal reserved Area 8, 7 address stro
APPENDIX: I/O MAP Register name Address Bit Name Function Setting 16-bit timer 0 comparison register A 0048180 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR0A15 CR0A14 CR0A13 CR0A12 CR0A11 CR0A10 CR0A9 CR0A8 CR0A7 CR0A6 CR0A5 CR0A4 CR0A3 CR0A2 CR0A1 CR0A0 16-bit timer 0 comparison data A CR0A15 = MSB CR0A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 0 comparison register B 0048182 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR0B15 CR0B14 CR0B13 CR0B1
APPENDIX: I/O MAP Register name Address Bit Name Function Setting 16-bit timer 1 comparison register A 0048188 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR1A15 CR1A14 CR1A13 CR1A12 CR1A11 CR1A10 CR1A9 CR1A8 CR1A7 CR1A6 CR1A5 CR1A4 CR1A3 CR1A2 CR1A1 CR1A0 16-bit timer 1 comparison data A CR1A15 = MSB CR1A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 1 comparison register B 004818A (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR1B15 CR1B14 CR1B13 CR1B1
APPENDIX: I/O MAP Register name Address Bit Name Function Setting 16-bit timer 2 comparison register A 0048190 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR2A15 CR2A14 CR2A13 CR2A12 CR2A11 CR2A10 CR2A9 CR2A8 CR2A7 CR2A6 CR2A5 CR2A4 CR2A3 CR2A2 CR2A1 CR2A0 16-bit timer 2 comparison data A CR2A15 = MSB CR2A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 2 comparison register B 0048192 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR2B15 CR2B14 CR2B13 CR2B1
APPENDIX: I/O MAP Register name Address Bit Name Function Setting 16-bit timer 3 comparison register A 0048198 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR3A15 CR3A14 CR3A13 CR3A12 CR3A11 CR3A10 CR3A9 CR3A8 CR3A7 CR3A6 CR3A5 CR3A4 CR3A3 CR3A2 CR3A1 CR3A0 16-bit timer 3 comparison data A CR3A15 = MSB CR3A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 3 comparison register B 004819A (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR3B15 CR3B14 CR3B13 CR3B1
APPENDIX: I/O MAP Register name Address Bit Name Function Setting 16-bit timer 4 comparison register A 00481A0 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR4A15 CR4A14 CR4A13 CR4A12 CR4A11 CR4A10 CR4A9 CR4A8 CR4A7 CR4A6 CR4A5 CR4A4 CR4A3 CR4A2 CR4A1 CR4A0 16-bit timer 4 comparison data A CR4A15 = MSB CR4A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 4 comparison register B 00481A2 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR4B15 CR4B14 CR4B13 CR4B1
APPENDIX: I/O MAP Register name Address Bit Name Function Setting 16-bit timer 5 comparison register A 00481A8 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR5A15 CR5A14 CR5A13 CR5A12 CR5A11 CR5A10 CR5A9 CR5A8 CR5A7 CR5A6 CR5A5 CR5A4 CR5A3 CR5A2 CR5A1 CR5A0 16-bit timer 5 comparison data A CR5A15 = MSB CR5A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 5 comparison register B 00481AA (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR5B15 CR5B14 CR5B13 CR5B1
APPENDIX: I/O MAP Register name Address Bit IDMA base address loworder register 0048200 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IDMA base address high-order register 0048202 DF–C – (HW) DB DBASEH11 DA DBASEH10 D9 DBASEH9 D8 DBASEH8 D7 DBASEH7 D6 DBASEH6 D5 DBASEH5 D4 DBASEH4 D3 DBASEH3 D2 DBASEH2 D1 DBASEH1 D0 DBASEH0 reserved IDMA base address high-order 12 bits (Initial value: 0x0C003A0) IDMA start register 0048204 (B) D7 DSTART D6–0 DCHN IDMA start IDMA channel number 1 IDMA sta
APPENDIX: I/O MAP Register name Address Bit Name High-speed DMA Ch.0 transfer counter register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC0_L7 TC0_L6 TC0_L5 TC0_L4 TC0_L3 TC0_L2 TC0_L1 TC0_L0 BLKLEN07 BLKLEN06 BLKLEN05 BLKLEN04 BLKLEN03 BLKLEN02 BLKLEN01 BLKLEN00 Ch.0 transfer counter[7:0] (block transfer mode) DF DE DUALM0 D0DIR DD–8 D7 D6 D5 D4 D3 D2 D1 D0 – TC0_H7 TC0_H6 TC0_H5 TC0_H4 TC0_H3 TC0_H2 TC0_H1 TC0_H0 Ch.0 address mode selection D) Invalid S) Ch.
APPENDIX: I/O MAP Register name Address Bit High-speed 0048228 DMA Ch.0 (HW) low-order destination address set-up register DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 D0ADRL15 D) Ch.0 destination address[15:0] D0ADRL14 S) Invalid D0ADRL13 D0ADRL12 D0ADRL11 D0ADRL10 D0ADRL9 D0ADRL8 D0ADRL7 D0ADRL6 D0ADRL5 D0ADRL4 D0ADRL3 D0ADRL2 D0ADRL1 D0ADRL0 DF DE D0MOD1 D0MOD0 Ch.0 transfer mode DD DC D0IN1 D0IN0 D) Ch.
APPENDIX: I/O MAP Register name Address Bit Name High-speed DMA Ch.1 transfer counter register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC1_L7 TC1_L6 TC1_L5 TC1_L4 TC1_L3 TC1_L2 TC1_L1 TC1_L0 BLKLEN17 BLKLEN16 BLKLEN15 BLKLEN14 BLKLEN13 BLKLEN12 BLKLEN11 BLKLEN10 Ch.1 transfer counter[7:0] (block transfer mode) DF DE DUALM1 D1DIR DD–8 D7 D6 D5 D4 D3 D2 D1 D0 – TC1_H7 TC1_H6 TC1_H5 TC1_H4 TC1_H3 TC1_H2 TC1_H1 TC1_H0 Ch.1 address mode selection D) Invalid S) Ch.
APPENDIX: I/O MAP Register name Address Bit High-speed 0048238 DMA Ch.1 (HW) low-order destination address set-up register DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 D1ADRL15 D) Ch.1 destination address[15:0] D1ADRL14 S) Invalid D1ADRL13 D1ADRL12 D1ADRL11 D1ADRL10 D1ADRL9 D1ADRL8 D1ADRL7 D1ADRL6 D1ADRL5 D1ADRL4 D1ADRL3 D1ADRL2 D1ADRL1 D1ADRL0 DF DE D1MOD1 D1MOD0 Ch.1 transfer mode DD DC D1IN1 D1IN0 D) Ch.
APPENDIX: I/O MAP Register name Address Bit Name High-speed DMA Ch.2 transfer counter register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC2_L7 TC2_L6 TC2_L5 TC2_L4 TC2_L3 TC2_L2 TC2_L1 TC2_L0 BLKLEN27 BLKLEN26 BLKLEN25 BLKLEN24 BLKLEN23 BLKLEN22 BLKLEN21 BLKLEN20 Ch.2 transfer counter[7:0] (block transfer mode) DF DE DUALM2 D2DIR DD–8 D7 D6 D5 D4 D3 D2 D1 D0 – TC2_H7 TC2_H6 TC2_H5 TC2_H4 TC2_H3 TC2_H2 TC2_H1 TC2_H0 Ch.2 address mode selection D) Invalid S) Ch.
APPENDIX: I/O MAP Register name Address Bit High-speed 0048248 DMA Ch.2 (HW) low-order destination address set-up register DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 D2ADRL15 D) Ch.2 destination address[15:0] D2ADRL14 S) Invalid D2ADRL13 D2ADRL12 D2ADRL11 D2ADRL10 D2ADRL9 D2ADRL8 D2ADRL7 D2ADRL6 D2ADRL5 D2ADRL4 D2ADRL3 D2ADRL2 D2ADRL1 D2ADRL0 DF DE D2MOD1 D2MOD0 Ch.2 transfer mode DD DC D2IN1 D2IN0 D) Ch.
APPENDIX: I/O MAP Register name Address Bit Name High-speed DMA Ch.3 transfer counter register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC3_L7 TC3_L6 TC3_L5 TC3_L4 TC3_L3 TC3_L2 TC3_L1 TC3_L0 BLKLEN37 BLKLEN36 BLKLEN35 BLKLEN34 BLKLEN33 BLKLEN32 BLKLEN31 BLKLEN30 Ch.3 transfer counter[7:0] (block transfer mode) DF DE DUALM3 D3DIR DD–8 D7 D6 D5 D4 D3 D2 D1 D0 – TC3_H7 TC3_H6 TC3_H5 TC3_H4 TC3_H3 TC3_H2 TC3_H1 TC3_H0 Ch.3 address mode selection D) Invalid S) Ch.
APPENDIX: I/O MAP Register name Address Bit High-speed 0048258 DMA Ch.3 (HW) low-order destination address set-up register DF DE DD DC DB DA D9 A8 D7 D6 D5 D4 D3 D2 D1 D0 D3ADRL15 D) Ch.3 destination address[15:0] D3ADRL14 S) Invalid D3ADRL13 D3ADRL12 D3ADRL11 D3ADRL10 D3ADRL9 D3ADRL8 D3ADRL7 D3ADRL6 D3ADRL5 D3ADRL4 D3ADRL3 D3ADRL2 D3ADRL1 D3ADRL0 DF DE D3MOD1 D3MOD0 Ch.3 transfer mode DD DC D3IN1 D3IN0 D) Ch.
APPENDIX: I/O MAP Register name Address Bit Name Function Setting Communications 0200000 D15–2 – macro select (HW) D1 MCRS1 register D0 MCRS0 – Master configuration selection Software reset register – Reset PHS communications block 1 Reset Reset PDC communications block 1 Reset Reset HDLC communications block 1 Reset – – Specify clock frequency divider for communications block – 0200002 D15–3 – (HW) D2 PHSRST D1 PDCRST D0 HDLRST Communications 0200004 D15-4 – block clock (HW) D3 CKD3 frequency
APPENDIX: I/O MAP Register name Address Bit Name Function Setting Communications 0200028 D15–5 – block CP4 (HW) D4 CP4EN4 interrupt select D3 CP4EN3 register D2 CP4EN2 D1 CP4EN1 D0 CP4EN0 – Map UINT4 interrupt requests to CP4 Map UINT3 interrupt requests to CP4 Map UINT2 interrupt requests to CP4 Map UINT1 interrupt requests to CP4 Map UINT0 interrupt requests to CP4 1 1 1 1 1 Enable Enable Enable Enable Enable Communications 020002A D15–12 – D11 RI block modem (HW) D10 CTS status register D9 DCD
APPENDIX: I/O MAP Register name Address Bit Name Function HDLC interrupt 0200302 D15–8 – control register (HW) D7 ERES D6 RESINT D5–2 – D1 RRXINT D0 RTXINT – HDLC error reset HDLC E/S interrupt reset – HDLC receive interrupt reset HDLC transmit interrupt reset HDLC interrupt 0200304 D15–8 – enable settings (HW) D7 ABRTIES register D6 TXUEIES D5 HUNTIES D4 IDLDIES D3–0 – – Enable Abort interrupt setting Enable TXUDR interrupt setting Enable Hunt interrupt setting Enable idle detection interrupt setti
APPENDIX: I/O MAP Register name Address Bit Name Function Setting Init.
APPENDIX: I/O MAP Register name Address HDLC residue code register Bit Name 0200332 D15–8 – (HW) D7 RCODE7 D6 RCODE6 D5 RCODE5 D4 RCODE4 D3 RCODE3 D2 RCODE2 D1 RCODE1 D0 RCODE0 Function Setting Init. R/W Remarks – RCODE[7:0] Residue Code 11111110 Number of valid bits in excess residue code bits at end of frame 11111100 11111000 11110000 11100000 11000000 10000000 – Effective bits 7 6 5 4 3 2 1 – X X X X X X X X – R 0 when being read.
International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. EPSON (CHINA) CO., LTD. - HEADQUARTERS 150 River Oaks Parkway San Jose, CA 95134, U.S.A. Phone: +1-408-922-0200 Fax: +1-408-922-0238 23F, Beijing Silver Tower 2# North RD DongSanHuan ChaoYang District, Beijing, CHINA Phone: 64106655 Fax: 64107319 SHANGHAI BRANCH 7F, High-Tech Bldg., 900, Yishan Road, Shanghai 200233, CHINA Phone: 86-21-5423-5577 Fax: 86-21-5423-4677 - SALES OFFICES West 1960 E.
In pursuit of “Saving” Technology, Epson electronic devices. Our lineup of semiconductors, displays and quartz devices assists in creating the products of our customers’ dreams. Epson IS energy savings.
S1C33210 Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epsondevice.
