Specifications

6 Board Development

EPSON

S1C33 ASIC DESIGN GUIDE

EMBEDDED ARRAY S1X50000 SERIES

(2) Board development process (example 2)

Use the following procedure when the package and pin arrangement cannot be determined

initially.

Step 1: Create an evaluation board using the C33209 (general-purpose product), FPGA, and

the required memory. Evaluate the performance and the FPGA circuit. Also, start

software development at this time.

Step 2: Create the target board (mass production version), and at the same time design and

manufacture the C33 ASIC.

Step 3: Mount the C33 ASIC on the target board, verify software operation, and perform final

evaluation.

Step 4: Release to production.

Figure 6.5 Board Development Structure (Example 2)

SRAM

FPGA

S1C33209

or else

Flash

QFP I/F

others

Either S1C33209 that includes an FPGA or

a circuit block equivalent to that product

S1C33209 pin

pattern

ROM. RAM, flash memory,

G/A, and other devices

Target board (mass production version)

Target board (evaluation version)

Pin pattern for the IC

with internal S1C33

macros

ROM. RAM, flash memory,

G/A, and other devices

For mass production

During board and

software development

S1C33 CPU, BCU basic

peripheral functions, and

internal RAM

C33 ASIC manufacturing

C33 ASIC product

Internal ROM

emulation