Specifications

6 Board Development

S1C33 ASIC DESIGN GUIDE

EPSON

EMBEDDED ARRAY S1X50000 SERIES

(1) Board development process (example 1)

Step 1: Determine the C33 ASIC product package and pin arrangement.

Step 2: Perform performance and user circuit evaluation by creating a target board (mass

production version), and, at the same time, creating an EPOD board with an FPGA by

using a C33209 (a general-purpose product). Also, start software development.

Step 3: Design and manufacture the C33 ASIC product.

Step 4: Mount the C33 ASIC product in the target board, verify software operation, and

perform final evaluation.

Step 5: Release to production.

Figure 6.4 Board Development Structure (Example 1)

FPGA

S5U1C33XXXE that includes an FPGA and provides a QFP interface

Pad pattern for the IC

with internal S1C33

macros

ROM. RAM, flash memory, G/A, and other devices

For mass production

Target board (mass production version)

SRAM

S1C33209

or else

Flash

QFP I/F

others

During board and

software development

S1C33 CPU, BCU basic

peripheral functions, and

internal RAM

C33 ASIC manufacturing

C33 ASIC product

Internal ROM

emulation