Specifications

5 Simulation
S1C33 ASIC DESIGN GUIDE
EPSON
75
EMBEDDED ARRAY S1X50000 SERIES
csh> grep //_ _ samplex_f10emux1.tb
//_
_.../sim/verilog/ENV/tb/header.tb
//_
_.../sim/verilog/ENV/tb/c33_chip.tb
//_
_.../sim/verilog/ENV/tb/pll_00.tb
//_
_.../sim/verilog/ENV/tb/c33_init.tb
//_
_.../sim/verilog/ENV/tb/osc1_5MHz.tb
//_
_.../sim/verilog/ENV/tb/mode_x1spd.tb
//_
_.../sim/verilog/ENV/tb/ea10md_00.tb
//_
_.../sim/verilog/ENV/tb/ea3md_0.tb
//_
_.../sim/verilog/ENV/tb/mode_normal.tb
//_
_.../sim/verilog/ENV/tb/top1.tb
//_
_.../sim/verilog/Sample/t0/tb/cpu_trace.tb
( "..." indicates the actual installation directory.)
The c33_sim.csh script replaces the character string "TRACE_FILE" in the test bench with the
name of the output file name specified by tb = option. Therefore, it is possible to output a trace
file or a waveform file with the name of the output file using a common test bench component file.