Specifications

5 Simulation
S1C33 ASIC DESIGN GUIDE
EPSON
73
EMBEDDED ARRAY S1X50000 SERIES
5.5.3 Simulation Execution Script
The C33 simulation is executed by the following script.
$C33/sim/verilog/Sample/t0/verilog.boo
$C33/sim/verilog/Sample/t0/qa_sample.csh
$C33/sim/verilog/ENV/bin/c33_sim.csh
The file verilog.boo is a shell script that sets up the Verilog simulator startup command options
and actually starts the Verilog simulator.
The file qa_sample.csh is a script that prepares to manage the operations associated with running
the simulation using the file c33_sim.csh.
The file c33_sim.csh executes the following sequence of operations.
• Generates the C33 machine language code that is read into the Verilog ROM model.
• Generates the test bench for the Verilog simulation.
• Starts the Verilog simulator using the verilog.boo file.
Format of the file c33_sim.csh
c33_sim.csh ASM file [option...]
ASM_file: Name of the C33 assembler program file
The following options can be used.
(There must be no spaces around the equal signs (=) in the options.)
trc=file : Specifies the name of the file to which the trace results are output.
cycle=n : Specifies the number of simulation execution cycles.
tcyc=n : Specifies the cycle time for the simulation. (Units: ns)
tb=file : Specifies a test bench component file. This option may be used
multiple times.
incl=file : Specifies a file that lists test bench component files. This option
may be used in conjunction with the tb= option. This option may
be used multiple times.
debug : Used to debug the test bench environment. The verilog.boo
file is not run if this option is specified.