Specifications

5 Simulation

S1C33 ASIC DESIGN GUIDE

EPSON

EMBEDDED ARRAY S1X50000 SERIES

Figure 5.2 Simulation Flowchart

Note: Current there is only a gate level simulation model.

Table 5.1 Simulation Conditions

Simulation condition

C33 hard macros

(CPU core, DMA)

User logic, C33 soft macros

T0 timing No SDF No SDF

Forward Annotation Assumed wiring SDF Assumed wiring SDF

Back Annotation Post-layout SDF Post-layout SDF

Test bench creation script

Verilog netlist C33 MACRO

C33 ASM code

C33 Assembler

LST2ROM

ROM code

Stimulus

Test Bench

EPSON Lib

Verilog-XL

Trace file

Waveform display file

External memory model

(SRAM,DRAM)