Specifications

5 Simulation
68
EPSON
S1C33 ASIC DESIGN GUIDE
EMBEDDED ARRAY SSL50000 SERIES
Chapter 5 Simulation
5.1 Design Flowchart
Figure 5.1 Design Flowchart
Bulk Design
Development specification
verification
Preliminary Net P&R
Bulk signoff
User circuit development
Logic verification
Metal design
C33 Vector verification
Metal signoff
RTL coding
Logic synthesis
Pre-simulation
Logic simulation
Post-simulation
Bulk Design
Development specification
verification
Preliminary Net P&R
Bulk signoff
User circuit development
Logic verification
Metal design
C33 Vector verification
Metal signoff
RTL coding
Logic synthesis
Pre-simulation
Logic simulation
Post-simulation