Specifications

1 Product Overview
S1C33 ASIC DESIGN GUIDE
EPSON
1
EMBEDDED ARRAY S1X50000 SERIES
Chapter 1 Product Overview
1.1 Introduction
This product, abbreviated here as "C33," is an ASIC macro family that consists of Seiko Epson's
independently developed S1C33000 Series 32-bit CPU core and macros for a wide range of peripheral
functions. The C33 macros can be integrated on Seiko Epson's 0.35 µm embedded ASIC family
(S1X50000 Series) ICs. SRAM, ROM, and flash memory ASIC memory macros that share the same
process technology can be integrated on the same chip. Thus Seiko Epson provides a complete ASIC
microcontroller design environment, and makes ASIC products (S1C33ASIC) that include C33
macros available to our customers.
The C33 CPU features a RISC architecture. Despite the small size of this CPU core, it provides an
extremely powerful instruction set that allows compilers to generate compact code. The C33 macros
provide the following features.
• High speed and high performance: Operation from DC to 60 MHz. ASICs with on chip
ROM can operate at up to 50 MHz, and ASICs without
ROM can operate at up to 60 MHz.
• Powerful instruction set: 16-bit fixed length, 105 basic instructions.
• Instruction execution cycle: Most instructions are executed in a single cycle.
• Multiply and accumulate operation: 16 bits × 16 bits + 64 bits. Multiply and accumulate
operations are executed in 2 clock cycles,
thus achieving 25 MOPS at 50 MHz.
• Registers: Sixteen 32-bit general-purpose registers and five 32-bit
special registers.
• Address space: 256 MB linear address space (28-bit addresses) shared
by code, data, and I/O registers.
• External bus interface: 15 configurable memory areas
Direct connection to external memory.
• Interrupts: Reset, NMI, up to 128 external interrupts, 4 software
interrupts, and two instruction execution exceptions
• Reset: Cold reset, hot reset, and boot from area 10.
• Low-power modes: Sleep mode and halt mode.
• Harvard architecture: Instruction fetch and data load/store operations are
executed in parallel.
• User interface: Allows software controlled insertion of wait cycles
(up to 7 cycles).
Supports #WAIT pin handshake control.
Large memory space for user logic (up to 16M bytes)
BCU registers allow internal software access to areas 4
through 18.
Large numbers of interrupt request signals from the
user logic may be connected to the interrupt controller.