Specifications

4 Special Operations in ASICs that Include C33 Macros
S1C33 ASIC DESIGN GUIDE
EPSON
63
EMBEDDED ARRAY S1X50000 SERIES
4.3 Verifying the Constraints on the Pin Arrangement
The chip floorplan will differ depending on the chip size and the C33 macro modules selected. The
following constraints on the pin arrangement arise due to these variations. Please consult your Seiko
Epson ASIC representative when verifying the pin arrangement.
4.3.1 Constraints on PLL, Low-speed, and High-speed Oscillator
Circuit Pins
The positions of the PLL pin (P_PLLC) and the two high-speed oscillator circuit pins (P_OSC3 and
P_OSC4) depend on the layout of the C33 macros. The positions of the low-speed oscillator circuit
pins (P_OSC1 and P_OSC2) depend on the position of the low-speed oscillator circuit. These pins
should be flanked by either power supply pins or, at least by input pins whose values do not change.
(Refer to the example shown in figure 4.1.)
4.3.2 Constraints on A/D Converter Pins
The positions of the analog power supply (AV
DD
) and analog input pins (P_K60 to P_K67) depend
on the position of the A/D converter macro. While the A/D converter macro can be moved up, down,
left, or right on the chip, there are cases where its position is constrained by the size of the chip and
the positions of other macros. The power supply (AV
DD
) for the A/D converter macro and the A/D
converter I/O cells is isolated from the other power supplies (HV
DD
and LV
DD
). I/O cells for the
separate power supply flank the A/D converter I/O cells. This means that pins other than A/D
converter pins must not be located in the AV
DD
area. (Refer to the example shown in figure 4.1. Note
that only the V
DD
system is a separate power supply and that V
SS
is shared.)
4.3.3 Number of Power Supply Pins
Refer to the S1L50000 SERIES ASIC DESIGN GUIDE for details on the number of power supply
pins.
4.3.4 Floorplan
Figure 4.1 presents an example of the floorplan for a device for which all of the blocks (C33_CORE,
C33_DMA, C33_ADC, and C33_PERI) have been selected. Note that this figure is an example of a
floorplan, and does not indicate the relationships between the sizes of the blocks and I/O areas. As a
result, the actual sizes of the blocks and I/O areas on the chip differ from those shown.