Specifications

3 C33 Test Functions
S1C33 ASIC DESIGN GUIDE
EPSON
59
EMBEDDED ARRAY S1X50000 SERIES
3.3 User Circuit Test Mode (TST_USER mode)
3.3.1 Procedure to Enter Test Mode
The following presents the procedure entering test mode.
(1) With P_RESETX = 0 and P_TST = 0, input at least 4 clock cycles from P_OSC3 to
stabilize the C33 macro internal state. After that, set P_TST to 1. After that, system clock
input is disabled internally in the C33 macros.
(2) With P_RESETX = 0 and P_TST = 1, input 1 rising edge on the P_EA10M0 signal, which
is stable signal in normal mode. At this transition, C33 mode is determined to User Circuit
Test Mode, the TST_USER macro pin will switch from low to high.
(The TST_USER signal being at the high level indicates that the IC in User Circuit Test
Mode.)
(3) Set P_RESETX to 1.
Caution: Since it is possible for the chip to switch to another mode, be sure to hold all
input pins that can affect the initial state fixed at either the high or low level. The
following pins must be held fixed: P_NMI_X, P_X2SPD, P_EA10M1,
P_EA10M2, P_DSIO, P_PLLS0, P_PLLS1, and P_OSC1. In particular, the
P_NMI_X and P_DSIO must be held at their inactive state, namely the high
level.
Figure 3.3 Transition to User Circuit Test Mode
TST_USER
TST_USER mode
Furthermore,
C33 system clock input
is disabled.
P_TST
P_RESETX
P_EA10M0
P_OSC3
Input of at least 4 clock cycles