Specifications

3 C33 Test Functions

EPSON

S1C33 ASIC DESIGN GUIDE

EMBEDDED ARRAY S1X50000 SERIES

3.2.2 Test Mode

In the DC/AC test mode, the user I/O cells are controlled by the C33 macro user pin internal signals,

namely the TST_TA, TST_TE_X, and TST_TS signals. Note that when P_TST is high, the I/O pull-

up/pull-down resistors are set to the inactive state.

The control and output pins function as follows in this test mode.

Table 3.1 DC/AC Test Mode External Pin Functions

Measurement Mode Descriptions (The following descriptions are identical to those provided in the

S1L50000 SERIES DESIGN GUIDE.)

1) Quiescent current drain measurement mode

• High-impedance mode: bidirectional pins function as inputs, and 3-state outputs go to the

high-impedance state.

P_X2SPDX (IP0) ... Fixed at the high level

P_EA10M1 (IP1) ... Fixed at either high or low (Either can be selected.)

P_EA10M0 (IP2) ... Fixed at the high level

• Output mode: both bidirectional pins and 3-state output pins go to the output state.

P_X2SPDX (IP0 ... Fixed at the high level

P_EA10M1 (IP1) ... Fixed at either high or low (Either can be selected.)

P_EA10M0 (IP2) ... Fixed at the low level

2) Output characteristics (V

) measurement mode

P_X2SPDX (IP0) ... Fixed at the high level

P_EA10M1 (IP1) ... High level or low level input

This input state is output to all output cells and bidirectional cells (if

EA10MD0 is low).

P_EA10M0 (IP2) ... Controls the bidirectional pin mode.

High ... High-impedance (input) mode

Low ... Output mode

External pin I/O Function

P_X2SPDX In The TCIR IP0 pin

P_EA10M1 In The TCIR IP1 pin

P_EA10M0 In The TCIR IP2 pin

P_A1 Out Output pin for the special-purpose AC path measurement mode

P_BCLK Out Output pin for input logic level verification mode

Table 3.2 Test Mode Signals for DC/AC Test Mode

Macro internal signal I/O Function

tst_dct

Out Goes to 1 when the chip enters DC/AC test mode