Specifications

3 C33 Test Functions

S1C33 ASIC DESIGN GUIDE

EPSON

EMBEDDED ARRAY S1X50000 SERIES

3.2 DC/AC Test Mode (TST_DCT mode)

3.2.1 Procedure to Enter Test Mode

Use the following procedure entering test mode.

(1) With P_RESETX = 0 and P_TST = 0, input at least 4 clock cycles from P_OSC3 to

stabilize the C33 macro internal state. After that, set P_TST to 1.

(2) With P_RESETX = 0 and P_TST = 1, input 4 rising edges on the P_X2SPDX signal,

which is stable signal in normal mode.

(3) Set P_RESETX to 1. At this transition, C33 mode is determined to DC/AC Test Mode, the

C33 internal signal tst_dct will switch from low to high. (The tst_dct signal being at the

high level indicates that the IC in DC/AC Test Mode.)

Note that the tst_dct signal can be monitored by AAA.tst_dct.

Note 1: AAA is the instance name of the C33 macro.

Note 2: Since it is possible for the chip to switch to another mode, be sure to hold all

input pins that can affect the initial state fixed at either the high or low level.

The following pins must be held fixed: P_NMI_X, P_EA10M0, P_EA10M1,

P_EA10M2, P_DSIO, P_PLLS0, P_PLLS1, and P_OSC1. In particular, the

P_NMI_X and P_DSIO must be held at their inactive state, namely the high

level.

Figure 3.1 Transition to Test Mode

P_TST

P_RESETX

P_X2SPDX

AAA.tst_dct

P_OSC3

Input of at least 4 clock cycles

Test mode

DC/AC