Specifications

2 C33 Macro Specifications
48
EPSON
S1C33 ASIC DESIGN GUIDE
EMBEDDED ARRAY S1X50000 SERIES
SRAM write cycle (when wait cycles are inserted)
Input, output and I/O port timing
U_BCUCLK
U_ADDR[23:0]
U_CEx
U_WRH_X
U_DOUT[15:0]
U_WAIT_X
C1 Cw (wait cycle) Cw (wait cycle) Cn (last cycle)
tAD
tCE1 tCE2
tWRD2tWRD1
tWTS tWTH tWTS tWTStWTH tWTH
tWDD1 tWDH
tWRW
tAD
Wait cycle follows Last cycle follows
U_WRL_X/
U_BCLK
U_Kxx, Pxx
(input: data read
from the port)
U_Pxx (output)
U_Kxx
(K-port interrupt input)
t UINPS
t UKINW
t UINPH
t UOUTD
Valid input