Specifications

2 C33 Macro Specifications
S1C33 ASIC DESIGN GUIDE
EPSON
47
EMBEDDED ARRAY S1X50000 SERIES
SRAM read cycle (when a wait cycle is inserted)
∗
1
t
RDH is measured with respect to the first signal change (negation) of either the P_RD, P_CEx, or the
P_A[23:0] signals.
SRAM write cycle (basic cycle: 2 cycles)
U_BCUCLK
U_ADDR[23:0]
U_CEx
U_RD_X
U_DIN[15:0]
U_WAIT_X
C1 Cw (wait cycle) Cn (last cycle)
tAD
tCE1 tCE2
tRDD2tRDD1 (C1 only)
tRDAC1
tRDS
tWTS tWTHtWTS tWTH
tRDH
tCEAC1
tACC1
tRDW
tAD
*1
U_BCUCLK
U_ADDR[23:0]
U_CEx
U_DOUT[15:0]
U_WAIT_X
C1 C2
tAD
tCE1 tCE2
tWRD2tWRD1
tWTS tWTH
tWDD1 tWDH
tWRW
tAD
U_WRL_X/
U_WRH_X