Specifications

2 C33 Macro Specifications
46
EPSON
S1C33 ASIC DESIGN GUIDE
EMBEDDED ARRAY S1X50000 SERIES
Reset
SRAM read cycle (Basic cycle: 1 cycle)
∗
1
t
RDH is measured with respect to the first signal change (negation) of either the P_RD, P_CEx, or the
P_A[23:0] signals.
tURA
tURD
tURST
U_BCUCLK
U_RST_X
P_RESETX
U_BCUCLK
U_ADDR[23:0]
U_CEx
U_RD_
X
U_DIN[15:0]
U_WAIT_X
t C3
t AD
t CE1 t CE2
t RDD2 t RDD1
t RDAC1
t RDS
t WTS t WTH
t RDH
t CEAC1
t ACC1
t RDW
t AD
*1