Specifications

2 C33 Macro Specifications
S1C33 ASIC DESIGN GUIDE
EPSON
45
EMBEDDED ARRAY S1X50000 SERIES
2.6.6.6 AC Characteristics Timing Charts (User Logic Interface)
This section presents the timing charts for the interface between C33 macros and the user logic on the
same chip.
Clock signals
t C1
t C2
t C3
t UC1H
t UC1H
t UC1D=
t UCPH
t UPLL
t UCPD=
t UCBH
t UCBD=
t C3
t UC3H
t U3D=
t UPLL
t UC3H
t UCPH
t UCBH
t UPH
t UBH t UBL
t UPL
t UCBL
t UCPL
t CBCLK
t CBCLK
t UPH
t UPD=
t CPSC
t CBH
t UBD=
t CBCU
t CPSC
t CBCU
t UCDP
t UCDB
t UDP
t UDB
t UC1L
t UC3L
U_OSC1CLK
U_OSC3CLK
U_PLLCLK
U_BCLK
U_PERICLK
U_BCUCLK
(Default output)