Specifications

2 C33 Macro Specifications
44
EPSON
S1C33 ASIC DESIGN GUIDE
EMBEDDED ARRAY S1X50000 SERIES
Common Characteristics (User Logic Interface)
The V
DD
and V
SS
levels are always used for the interface with user logic.
(Unless otherwise specified: V
DD
=3.0V to 3.6V, V
SS
=0V, Ta=–40 to 85°C)
SRAM read cycle
(Unless otherwise specified: V
DD
=2.7V to 3.6V, V
SS
=0V, Ta=–40 to 85°C)
SRAM write cycle
(Unless otherwise specified: V
DD
=3.0V to 3.6V, V
SS
=0V, Ta=–40 to 85°C)
Input, Output, I/O Ports (User Logic Interface)
(Unless otherwise specified: V
DD
=3.0V to 3.6V, V
SS
=0V, Ta=–40 to 85°C)
Item Symbol Min. Max. Unit
*
Address delay time t
UAD
– 7 ns
U_CE
X
delay time (1) t
UCE1
– 7 ns
U_CE
X
delay time (2) t
UCE2
– 7 ns
Wait setup time t
UWTS
10 – ns
Wait hold time t
UWTH
0 – ns
Read signal delay time (1) t
URDD1
7 ns
Read data setup time t
URDS
13 ns
Read data hold time t
URDH
0 ns
Write signal delay time (1) t
UWRD1
7 ns
Write data delay time (1) t
UWDD1
7 ns
Write data delay time (2) t
UWDD2
0 7 ns
Write data hold time t
UWDH
0 ns
Item Symbol Min. Max. Unit
*
Read signal delay time (2) t
URDD2
7 ns
Read signal pulse width t
URDW
t
CYC
(0.5+WC)-7 ns
Read address access time (1) t
UACC1
t
CYC
(1+WC)-20 ns
Chip enable access time (1) t
UCEAC1
t
CYC
(1+WC)-20 ns
Read signal access time (1) t
URDAC1
t
CYC
(0.5+WC)-20 ns
Item Symbol Min. Max. Unit
*
Write signal delay time t
WRD2
7 ns
Write signal pulse width t
WRW
t
CYC
(1+WC)-7 ns
Item Symbol Min. Max. Unit
*
Input data setup time t
UINPS
10 ns
Input data hold time t
UINPH
5 ns
Output data delay time t
UOUTD
10 ns
K-port interrupt SLEEP, HALT2 mode t
UKINW
30 ns
input pulse width Others 2 × t
CYC
ns