Specifications

2 C33 Macro Specifications
S1C33 ASIC DESIGN GUIDE
EPSON
43
EMBEDDED ARRAY S1X50000 SERIES
2.6.6.5 AC Characteristics Tables (User Logic Interface)
The tables in this section stipulate the timing of the interface between the C33 macros and the user
logic on the same chip. (Note that these timing values must be verified by simulation at the end of the
development process.)
External clock input characteristic
This table stipulates the AC characteristics for V
DD
in the range 3.0 to 3.6 V.
Consult your Seiko Epson representative for details on AC characteristics under other conditions.
(Unless otherwise specified: V
DD
= 3.0 to 3.6 V, V
SS
= 0 V, Ta = -40 to 85°C)
Note 1: For the OSC1 clock cycle time, the frequency adjustment range is 50 ppm at f
OSC1
= 32.768 MHz. Refer to section
2.6.6.7, "Oscillator Characteristics" for details.
Note 2: The AC characteristics for the clocks shown above assume that the clocks are generated by the OSC1 and OSC3
oscillator circuits.
Item Symbol Min. Max. Unit
*
Low-speed clock cycle time t
C1
– – ns 1
U_OSC1CLK clock duty t
UC1D
45 55 %
High-speed clock cycle time t
C3
30 – ns
U_OSC3CLK clock duty t
U3D
40 60 %
U_PLLCLK clock cycle time t
UPLL
16.66 – ns
U_PLLCLK clock duty t
UCPD
40 60 %
U_PLLCLK clock delay time t
UCDP
– 5 ns
U_BCLK clock cycle time t
CBCLK
16.66 – ns
U_BCLK clock duty t
UCBD
40 60 %
U_BCLK clock delay time t
UCDB
– 13 ns
U_PERICLK clock cycle time t
CPSC
16.66 – ns
U_PERICLK clock duty t
VPD
40 60 %
U_PERICLK clock delay time t
UDP
– 10 ns
U_BCUCLK clock cycle time t
CBCU
16.66 – ns
U_BCUCLK clock duty t
UBD
40 60 %
U_BUCLK clock delay time t
UDB
– 10 ns
Reset assert delay time t
URA
– 10 ns
Reset deassert delay time t
URD
– 6 ns
Minimum reset pulse width t
URST
6 t
cyc
– ns