Specifications

2 C33 Macro Specifications
42
EPSON
S1C33 ASIC DESIGN GUIDE
EMBEDDED ARRAY S1X50000 SERIES
Burst ROM read cycle
∗1
t
RDH is measured with respect to the first signal change (negation) from among the P_RD, P_CEx, or the
P_A[23:0] signals.
External bus master and NMI timing
*1 eBUS_OUT indicates the following pins:
P_A[23:0], P_RD_X, P_WRL_X, P_WRH_X, P_HCAS_X, P_LCAS_X, P_CEx[17:4], P_D[15:0]
Input, output and I/O port timing
P_BCLK
P_A[23:2]
P_A[1:0]
P_CEx
P_RD_X
P_D[15:0]
SRAM read cycle Burst cycle Burst cycle Burst cycle
tAD tAD
tAD
tRDS
tRDAC2
tCEAC
tRDH
tCE2tCE1
tRDD2tRDD1
tAD tAD tAD tAD
tACC2
tRDS
tRDH
tACCB
tRDS
tRDH
tACCB
tRDS
tRDH
tACCB
*1
P_BCLK
P_P34(#BUSREQ)
P_P35(#BUSACK)
eBUS_OUT signals *1
eBUS_OUT signals *1
P_NMI
tBRQS
Valid input
tNMIW
tBRQH
tBAKD
tZ2E
tB2Z
P_BCLK
Kxx, Pxx
(input: data read
from the port)
Pxx, Rxx (output)
Kxx
(K-port interrupt input)
tINPS
Valid input
tKINW
tINPH
tOUTD