Specifications

2 C33 Macro Specifications
S1C33 ASIC DESIGN GUIDE
EPSON
41
EMBEDDED ARRAY S1X50000 SERIES
EDO DRAM page access cycle
∗
1
t
RDH is measured with respect to the first signal change from among the P_RD (negation), P_RASx
(negation), or the #CAS (fall) signals.
DRAM CAS-before-RAS refresh cycle
DRAM self-refresh cycle
P_BCLK
P_A[23:0]
P_CEx
P_HCAS_X/
P_LCAS_X
P_RD_X
P_D[15:0]
P_WRL_X
D[15:0]
RAS1
Data transfer #1 Data transfer #2 Next data transfer
CAS1 CAS2 PRE1 (precharge) RAS1'
tAD tAD tAD
tRDS
tACCE
tRACE
tRASD2tRASD1
tRDD3tRDD1
tWRD3tWRD1
tWDD1 tWDD2 tWDD2
tCACE
tACCE
tRASW
tRDW2
tCASD2tCASD1
tCASW
tWRW2
tRDH tRDS tRDH
*1
(RAS output)
(Read)
(Write)
P_BCLK
P_CEx
P_HCAS_X/
P_LCAS_X
P_WRL_X
CBR refresh cycle
CCBR1 CCBR2 CCBR3
tRASD2tRASD1
tCASD2tCASD1
(RAS output)
Self-refresh mode setup Self-refresh mode
tCASD2
Self-refresh mode canceration
tRASD2tRASD1
tCASD1
6-cycle precharge
(Fixed)
P_BCLK
P_CEx
P_HCAS_X/
P_LCAS_X
(RAS output)