Specifications

2 C33 Macro Specifications
40
EPSON
S1C33 ASIC DESIGN GUIDE
EMBEDDED ARRAY S1X50000 SERIES
DRAM fast-page access cycle
∗
1
t
RDH is measured with respect to the first signal change (negation) of either the P_RD or the P_A[23:0] sig-
nals.
EDO DRAM random access cycle (basic cycle)
∗
1
t
RDH is measured with respect to the first signal change (negation) of either the P_RD or the P_RASx signals.
RAS1
Data transfer #1 Data transfer #2 Next data transfer
CAS1 CAS2 PRE1 (precharge) RAS1'
tAD tAD tAD
tRDS
tACCF
tRACF
tRDH
tRASD2tRASD1
tRDD3tRDD1
tWRD3tWRD1
tWDD1 tWDD2 tWDD2
tCACF tACCF
tRASW
tRDW2
tCASD2tCASD1
tRDS tRDH
tCASW
tWRW2
*1*1
P_BCLK
P_A[23:0]
P_CEx
P_HCAS_X/
P_LCAS_X
P_RD_X
P_D[15:0]
P_WRL_X
P_D[15:0]
(RAS output)
(Read)
(Write)
RAS1
Data transfer #1
Next data transfer
CAS1 PRE1 (precharge) RAS1' CAS1'
tAD tAD tAD
tCASD2tCASD1
tRDS2
tACCE
tRACE
tRDH
tRASD2tRASD1
tRASW
tRDD3tRDD1
tRDW2
tWRD3tWRD1
tWRW2
tWDD1 tWDD2
tCASW
tCACE
*1
P_BCLK
P_A[23:0]
P_CEx
P_HCAS_X/
P_LCAS_X
P_RD_X
P_D[15:0]
P_WE
D[15:0]
(RAS output)
(Read)