Specifications

2 C33 Macro Specifications
S1C33 ASIC DESIGN GUIDE
EPSON
39
EMBEDDED ARRAY S1X50000 SERIES
SRAM write cycle (when wait cycles are inserted)
DRAM random access cycle (basic cycle)
∗1
t
RDH is measured with respect to the first signal change (negation) of either the P_RD or the P_A[23:0] sig-
nals.
P_BCLK
P_A[23:0]
P_CEx
P_WRx_X
P_D[15:0]
P_P30
C1 Cw (wait cycle) Cw (wait cycle) Cn (last cycle)
tAD
tCE1 tCE2
tWRD2tWRD1
tWTS tWTH tWTS tWTStWTH tWTH
tWDD1 tWDH
tWRW
tAD
Wait cycle follows Last cycle follows
(Wait input)
P_BCLK
P_A[23:0]
P_CEx
P_HCAS_X/
P_LCAS_X
P_RD_X
D[15:0]
P_WRL_X
P_D[15:0]
RAS1
Data transfer #1
Next data transfer
CAS1 PRE1 (precharge) RAS1' CAS1'
tAD tAD tAD
tCASD2tCASD1
tRDS
tACCF
tRACF
tRDH
tRASD2tRASD1
tRASW
tRDD3tRDD1
tRDW2
tWRD3tWRD1
tWRW2
tWDD1 tWDD2
tCASW
tCACF
*1
(Read)
(Write)
(RAS output)