Specifications

2 C33 Macro Specifications
38
EPSON
S1C33 ASIC DESIGN GUIDE
EMBEDDED ARRAY S1X50000 SERIES
SRAM read cycle (when a wait cycle is inserted)
∗1
tRDH is measured with respect to the first signal change (negation) from among the P_RD, P_CEx, or the
P_A[23:0] signals.
SRAM write cycle (basic cycle: 2 cycles)
P_BCLK
P_A[23:0]
P_CEx
P_RD_X
P_D[15:0]
P_P30
C1 Cw (wait cycle) Cn (last cycle)
tAD
tCE1 tCE2
tRDD2tRDD1 (C1 only)
tRDAC1
tRDS
tWTS tWTHtWTS tWTH
tRDH
tCEAC1
tACC1
tRDW
tAD
*1
(Wait input)
P_BCLK
P_A[23:0]
P_CEx
P_WRx_X
P_D[15:0]
P_P30
C1 C2
t AD
t CE1 t CE2
t WRD2 t WRD1
t WTS t WTH
t WDD1 t WDH
t WRW
t AD
(Wait input)