Specifications

2 C33 Macro Specifications
S1C33 ASIC DESIGN GUIDE
EPSON
37
EMBEDDED ARRAY S1X50000 SERIES
2.6.6.4 AC Characteristics Timing Charts (I/O Buffer Pins)
This section presents the timing charts for the interface between the C33 macros and chip-external
circuits.
Clock
SRAM read cycle (basic cycle: 1 cycle)
∗
1 tRDH is measured with respect to the first signal change (negation) from among the P_RD, P_CEx, or the
P_A[23:0] signals.
P_OSC3
(High-speed clock)
tC3
P_BCLK
(Clock output)
tC3
tC3H
tC3ED = tC3H/tC3
tC1ED = tC1H/tC1
P_OSC1
(Low-speed clock)
tC1
tC1H
tCBD = tCBH/tC3
P_BCLK
(Clock output)
tC3
tCBH
tCD1 tCD2
tIF tIR
(1) When an external clock is input (in x1 speed mode):
(2) When the high-speed oscillation circuit is used for the operating clock:
P_BCLK
P_A[23:0]
P_CEx
P_RD_X
P_D[15:0]
P_P30
tC3
tAD
tCE1 tCE2
tRDD2tRDD1
tRDAC1
tRDS
tWTS tWTH
tRDH
tCEAC1
tACC1
tRDW
tAD
*1
(Wait input)