Specifications

2 C33 Macro Specifications
34
EPSON
S1C33 ASIC DESIGN GUIDE
EMBEDDED ARRAY S1X50000 SERIES
Burst ROM read cycle
1) 3.3V/5.0V dual power source
(Unless otherwise specified: HV
DD
=4.5V to 5.5V, LV
DD
=2.7V to 3.6V, V
SS
=0V, Ta=–40 to 85°C)
2) 3.3V single power source
(Unless otherwise specified: V
DD
=2.7V to 3.6V, V
SS
=0V, Ta=–40 to 85°C)
3) 2.0V single power source
(Unless otherwise specified: V
DD
=1.8V to 2.2V, V
SS
=0V, Ta=–40 to 85°C)
External bus master and NMI
The #BUSRE0, #BUSACK, and #NMI symbols in the external bus master and NMI timing
stipulations in the following tables are to be interpreted as follows.
#BUSRE0: When the P_34 pin is set up as bus request signal input from an external bus master.
#BUSACK: When the P_35 pin is set up as the bus acknowledge signal output to an external bus
master.
#NMI: The P_NMI_X input
Item Symbol Min. Max. Unit
*
Read address access time (2) t
ACC2
t
CYC
(1+WC)-20 ns
Chip enable access time (2) t
CEAC2
t
CYC
(1+WC)-20 ns
Read signal access time (2) t
RDAC2
t
CYC
(0.5+WC)-20 ns
Burst address access time t
ACCB
t
CYC
(1+WC)-20 ns
Item Symbol Min. Max. Unit
*
Read address access time (2) t
ACC2
t
CYC
(1+WC)-25 ns
Chip enable access time (2) t
CEAC2
t
CYC
(1+WC)-25 ns
Read signal access time (2) t
RDAC2
t
CYC
(0.5+WC)-25 ns
Burst address access time t
ACCB
t
CYC
(1+WC)-25 ns
Item Symbol Min. Max. Unit
*
Read address access time (2) t
ACC2
t
CYC
(1+WC)-60 ns
Chip enable access time (2) t
CEAC2
t
CYC
(1+WC)-60 ns
Read signal access time (2) t
RDAC2
t
CYC
(0.5+WC)-60 ns
Burst address access time t
ACCB
t
CYC
(1+WC)-60 ns