Specifications

2 C33 Macro Specifications
S1C33 ASIC DESIGN GUIDE
EPSON
33
EMBEDDED ARRAY S1X50000 SERIES
EDO DRAM random access cycle and EDO DRAM page cycle
1) 3.3V/5.0V dual power source
(Unless otherwise specified: HV
DD
=4.5V to 5.5V, LV
DD
=2.7V to 3.6V, V
SS
=0V, Ta=–40 to 85°C)
2) 3.3V single power source
(Unless otherwise specified: V
DD
=2.7V to 3.6V, V
SS
=0V, Ta=–40 to 85°C)
3) 2.0V single power source
(Unless otherwise specified: V
DD
=1.8V to 2.2V, V
SS
=0V, Ta=–40 to 85°C)
Item Symbol Min. Max. Unit
*
Column address access time t
ACCE
t
CYC
(1.5+WC)-25 ns
#RAS access time t
RACE
t
CYC
(2+WC)-25 ns
#CAS access time t
CACE
t
CYC
(1+WC)-15 ns
Read data setup time t
RDS2
20 ns
Item Symbol Min. Max. Unit
*
Column address access time t
ACCE
t
CYC
(1.5+WC)-25 ns
#RAS access time t
RACE
t
CYC
(2+WC)-25 ns
#CAS access time t
CACE
t
CYC
(1+WC)-20 ns
Read data setup time t
RDS2
20 ns
Item Symbol Min. Max. Unit
*
Column address access time t
ACCE
t
CYC
(1.5+WC)-60 ns
#RAS access time t
RACE
t
CYC
(2+WC)-60 ns
#CAS access time t
CACE
t
CYC
(1+WC)-60 ns
Read data setup time t
RDS2
20 ns