Specifications

2 C33 Macro Specifications
32
EPSON
S1C33 ASIC DESIGN GUIDE
EMBEDDED ARRAY S1X50000 SERIES
3) 2.0V single power source
(Unless otherwise specified: VDD=1.8V to 2.2V, VSS=0V, Ta=–40 to 85°C)
DRAM random access cycle and DRAM fast-page cycle
1) 3.3V/5.0V dual power source
(Unless otherwise specified: HV
DD
=4.5V to 5.5V, LV
DD
=2.7V to 3.6V, V
SS
=0V, Ta=–40 to 85°C)
2) 3.3V single power source
(Unless otherwise specified: V
DD
=2.7V to 3.6V, V
SS
=0V, Ta=–40 to 85°C)
3) 2.0V single power source
(Unless otherwise specified: V
DD
=1.8V to 2.2V, V
SS
=0V, Ta=–40 to 85°C)
Item Symbol Min. Max. Unit
*
#RAS signal delay time (1) t
RASD1
20 ns
#RAS signal delay time (2) t
RASD2
20 ns
#RAS signal pulse width t
RASW
t
CYC
(2+WC)-20 ns
#CAS signal delay time (1) t
CASD1
20 ns
#CAS signal delay time (2) t
CASD2
20 ns
#CAS signal pulse width t
CASW
t
CYC
(0.5+WC)-20 ns
Read signal delay time (3) t
RDD3
20 ns
Read signal pulse width (2) t
RDW2
t
CYC
(2+WC)-20 ns
Write signal delay time (3) t
WRD3
20 ns
Write signal pulse width (2) t
WRW2
t
CYC
(2+WC)-20 ns
Item Symbol Min. Max. Unit
*
Column address access time t
ACCF
t
CYC
(1+WC)-25 ns
#RAS access time t
RACF
t
CYC
(1.5+WC)-25 ns
#CAS access time t
CACF
t
CYC
(0.5+WC)-25 ns
Item Symbol Min. Max. Unit *
Column address access time t
ACCF
t
CYC
(1+WC)-25 ns
#RAS access time t
RACF
t
CYC
(1.5+WC)-25 ns
#CAS access time t
CACF
t
CYC
(0.5+WC)-25 ns
Item Symbol Min. Max. Unit
*
Column address access time t
ACCF
t
CYC
(1+WC)-60 ns
#RAS access time t
RACF
t
CYC
(1.5+WC)-60 ns
#CAS access time t
CACF
t
CYC
(0.5+WC)-60 ns