Specifications

2 C33 Macro Specifications
S1C33 ASIC DESIGN GUIDE
EPSON
31
EMBEDDED ARRAY S1X50000 SERIES
DRAM access cycle common characteristics
The #RAS and #CAS symbols in the stipulations for the DRAM interface in the following tables are
to be interpreted as follows.
• #RAS refers to that signal any one of the chip enable signals (P_CE
X
signals) set up by the
bus controller (BCU) to operate as a RAS signal for the DRAM.
• #CAS refers to the P_HCAS_X or the P_LCAS_X signal.
1) 3.3V/5.0V dual power source
(Unless otherwise specified: HV
DD
=4.5V to 5.5V, LV
DD
=2.7V to 3.6V, V
SS
=0V, Ta=–40 to 85°C)
2) 3.3V single power source
(Unless otherwise specified: V
DD
=2.7V to 3.6V, V
SS
=0V, Ta=–40 to 85°C)
Item Symbol Min. Max. Unit
*
#RAS signal delay time (1) t
RASD1
10 ns
#RAS signal delay time (2) t
RASD2
10 ns
#RAS signal pulse width t
RASW
t
CYC
(2+WC)-10 ns
#CAS signal delay time (1) t
CASD1
10 ns
#CAS signal delay time (2) t
CASD2
10 ns
#CAS signal pulse width t
CASW
t
CYC
(0.5+WC)-5 ns
Read signal delay time (3) t
RDD3
10 ns
Read signal pulse width (2) t
RDW2
t
CYC
(2+WC)-10 ns
Write signal delay time (3) t
WRD3
10 ns
Write signal pulse width (2) t
WRW2
t
CYC
(2+WC)-10 ns
Item Symbol Min. Max. Unit
*
#RAS signal delay time (1) t
RASD1
10 ns
#RAS signal delay time (2) t
RASD2
10 ns
#RAS signal pulse width t
RASW
t
CYC
(2+WC)-10 ns
#CAS signal delay time (1) t
CASD1
10 ns
#CAS signal delay time (2) t
CASD2
10 ns
#CAS signal pulse width t
CASW
t
CYC
(0.5+WC)-10 ns
Read signal delay time (3) t
RDD3
10 ns
Read signal pulse width (2) t
RDW2
t
CYC
(2+WC)-10 ns
Write signal delay time (3) t
WRD3
10 ns
Write signal pulse width (2) t
WRW2
t
CYC
(2+WC)-10 ns