Specifications

2 C33 Macro Specifications
30
EPSON
S1C33 ASIC DESIGN GUIDE
EMBEDDED ARRAY S1X50000 SERIES
2) 3.3V single power source
(Unless otherwise specified: V
DD
=2.7V to 3.6V, V
SS
=0V, Ta=–40 to 85°C)
3) 2.0V single power source
(Unless otherwise specified: V
DD
=1.8V to 2.2V, V
SS
=0V, Ta=–40 to 85°C)
SRAM write cycle
1) 3.3V/5.0V dual power source
(Unless otherwise specified: HV
DDE
=4.5V to 5.5V, LV
DD
=2.7V to 3.6V, V
SS
=0V, Ta=–40 to 85°C)
2) 3.3V single power source
(Unless otherwise specified: V
DD
=2.7V to 3.6V, V
SS
=0V, Ta=–40 to 85°C)
3) 2.0V single power source
(Unless otherwise specified: V
DD
=1.8V to 2.2V, V
SS
=0V, Ta=–40 to 85°C)
Item Symbol Min. Max. Unit
*
Read signal delay time (2) t
RDD2
10 ns
Read signal pulse width t
RDW
t
CYC
(0.5+WC)-10 ns
Read address access time (1) t
ACC1
t
CYC
(1+WC)-25 ns
Chip enable access time (1) t
CEAC1
t
CYC
(1+WC)-25 ns
Read signal access time (1) t
RDAC1
t
CYC
(0.5+WC)-25 ns
Item Symbol Min. Max. Unit
*
Read signal delay time (2) t
RDD2
10 ns
Read signal pulse width t
RDW
t
CYC
(0.5+WC)-10 ns
Read address access time (1) t
ACC1
t
CYC
(1+WC)-60 ns
Chip enable access time (1) t
CEAC1
t
CYC
(1+WC)-60 ns
Read signal access time (1) t
RDAC1
t
CYC
(0.5+WC)-60 ns
Item Symbol Min. Max. Unit
*
Write signal delay time (2) t
WRD2
8 ns
Write signal pulse width t
WRW
t
CYC
(1+WC)-10 ns
Item Symbol Min. Max. Unit
*
Write signal delay time (2) t
WRD2
10 ns
Write signal pulse width t
WRW
t
CYC
(1+WC)-10 ns
Item Symbol Min. Max. Unit
*
Write signal delay time (2) t
WRD2
20 ns
Write signal pulse width t
WRW
t
CYC
(1+WC)-20 ns