Specifications

2 C33 Macro Specifications
S1C33 ASIC DESIGN GUIDE
EPSON
29
EMBEDDED ARRAY S1X50000 SERIES
2) 3.3V single power source
(Unless otherwise specified: V
DD
=2.7V to 3.6V, V
SS
=0V, Ta=–40 to 85°C)
3) 2.0V single power source
(Unless otherwise specified: V
DD
= 1.8V to 2.2V, V
SS
=0V, Ta=–40 to 85°C)
SRAM read cycle
1) 3.3/5.0V dual power source
(Unless otherwise specified: HV
DD
=4.5V to 5.5V, LV
DD
=2.7V to 3.6V, V
SS
=0V, Ta=–40 to 85°C)
Item Symbol Min. Max. Unit
*
Address delay time t
AD
– 10 ns
P_CEx delay time (1) t
CE1
– 10 ns
P_CEx delay time (2) t
CE2
– 10 ns
Wait setup time t
WTS
15 – ns
Wait hold time t
WTH
0 – ns
Read signal delay time (1) t
RDD1
10 ns
Read data setup time t
RDS
15 ns
Read data hold time t
RDH
0 ns
Write signal delay time (1) t
WRD1
10 ns
Write data delay time (1) t
WDD1
10 ns
Write data delay time (2) t
WDD2
0 10 ns
Write data hold time t
WDH
0 ns
Item Symbol Min. Max. Unit
*
Address delay time t
AD
– 20 ns
P_CEx delay time (1) t
CE1
– 20 ns
P_CEx delay time (2) t
CE2
– 20 ns
Wait setup time t
WTS
40 – ns
Wait hold time t
WTH
0 – ns
Read signal delay time (1) t
RDD1
20 ns
Read data setup time t
RDS
40 ns
Read data hold time t
RDH
0 ns
Write signal delay time (1) t
WRD1
20 ns
Write data delay time (1) t
WDD1
20 ns
Write data delay time (2) t
WDD2
0 20 ns
Write data hold time t
WDH
0 ns
Item Symbol Min. Max. Unit
*
Read signal delay time (2) t
RDD2
8 ns
Read signal pulse width t
RDW
t
CYC
(0.5+WC)-8 ns
Read address access time (1) t
ACC1
t
CYC
(1+WC)-20 ns
Chip enable access time (1) t
CEAC1
t
CYC
(1+WC)-20 ns
Read signal access time (1) t
RDAC1
t
CYC
(0.5+WC)-20 ns