Specifications

2 C33 Macro Specifications
S1C33 ASIC DESIGN GUIDE
EPSON
27
EMBEDDED ARRAY S1X50000 SERIES
2.6.6.3 AC Characteristics Tables (I/O Buffer Pins)
The tables in this section stipulate the timing of the interface between the C33 macros and circuits
external to the chip.
External clock input characteristics
Note: These AC characteristics apply to input signals from outside the IC.
1) 3.3V/5.0V dual power source
(Unless otherwise specified: HV
DD
=4.5V to 5.5V, LV
DD
=2.7V to 3.6V, V
SS
=0V, Ta=–40 to 85°C)
Note: The input to the OSC3 pin must be in the range V
SS
to LV
DD
.
2) 3.3V single power source
(Unless otherwise specified: V
DD
=2.7V to 3.6V, V
SS
=0V, Ta=–40 to 85°C)
Note: The input to the OSC3 pin must be in the range V
SS
to V
DD
.
3) 2.0V single power source
(Unless otherwise specified: V
DD
=1.8V to 2.2V, V
SS
=0V, Ta=–40 to 85°C)
Note: The input to the OSC3 pin must be in the range V
SS
to V
DD
.
Item Symbol Min. Max. Unit
*
High-speed clock cycle time t
C3
30 ns
P_OSC3 clock input duty t
C3ED
45 55 %
P_OSC3 clock input rise time t
IF
5 ns
P_OSC3 clock input fall time t
IR
5 ns
P_BCLK high-level output delay time t
CD1
35 ns
P_BCLK low-level output delay time t
CD2
35 ns
Minimum reset pulse width (P_RESETX input) t
RST
6 × t
CYC
ns
Item Symbol Min. Max. Unit
*
High-speed clock cycle time t
C3
30 ns
P_OSC3 clock input duty t
C3ED
45 55 %
P_OSC3 clock input rise time t
IF
5 ns
P_OSC3 clock input fall time t
IR
5 ns
P_BCLK high-level output delay time t
CD1
35 ns
P_BCLK low-level output delay time t
CD2
35 ns
Minimum reset pulse width (P_RESETX input) t
RST
6×t
CYC
ns
Item Symbol Min. Max. Unit
*
High-speed clock cycle time t
C3
30 ns
P_OSC3 clock input duty t
C3ED
45 55 %
P_OSC3 clock input rise time t
IF
5 ns
P_OSC3 clock input fall time t
IR
5 ns
P_BCLK high-level output delay time t
CD1
60 ns
P_BCLK low-level output delay time t
CD2
60 ns
Minimum reset pulse width (P_RESETX input) t
RST
6 × t
CYC
ns