Specifications

2 C33 Macro Specifications
S1C33 ASIC DESIGN GUIDE
EPSON
25
EMBEDDED ARRAY S1X50000 SERIES
2.6.6.1 Symbol Description
tCYC: Bus-clock cycle time
• In x1 mode, t
CYC
= 50 nS (20 MHz) when the CPU is operated with a 20-MHz clock
t
CYC
= 30 nS (33 MHz) when the CPU is operated with a 33-MHz clock
• In x2 mode, t
CYC
= 50 nS (20 MHz) when the CPU is operated with a 40-MHz clock
t
CYC
= 40 nS (25 MHz) when the CPU is operated with a 50-MHz clock
t
CYC
= 33 nS (30 MHz) when the CPU is operated with a 60-MHz clock
WC: Number of wait cycles
Up to 7 wait cycles can be specified using the BCU control register. It is also possible to extend the
number of wait cycles by inputs (wait request inputs) to the P_P30 (#WAIT) pin or the U_WAIT_X
pin when it is necessary.
The minimum number of read cycles with no wait (0) inserted is 1 cycle.
The minimum number of write cycles with no wait cycle (0) inserted is 2 cycles. It does not change
even if 1-wait cycle is set. The write cycle is actually extended when 2 or more wait cycles are set.
When inserting wait cycles by controlling the wait request inputs from external circuits, the
sampling timing of the wait request input requires careful attention. Read cycles are terminated on
the cycle that the negation of the wait request input was sampled. Write cycles are terminated on
the cycle following the cycle that the negation of the wait request input was sampled.
C1, C2, C3, Cn: Cycle number
C1 indicates the first cycle when the BCU transfers data from/to an external memory or another
device. Similarly, C2 and Cn indicate the second cycle and nth cycle, respectively.
Cw: Wait cycle
Indicates that the cycle is wait cycle inserted.