Specifications

2 C33 Macro Specifications
20
EPSON
S1C33 ASIC DESIGN GUIDE
EMBEDDED ARRAY S1X50000 SERIES
2.6.3 DC Characteristics
1) 3.3V/5.0V dual power source
(Unless otherwise specified: HV
DD
=4.5V to 5.5V, LV
DD
=2.7V to 3.6V, V
SS
=0V, Ta=–40 to +85°C)
2) 3.3V single power source
(Unless otherwise specified: V
DD
=2.7V to 3.6V, V
SS
=0V, Ta=–40 to +85°C)
Item Symbol Condition Min. Typ. Max. Unit
*
Input leakage current I
LI
-1 – 1 µA
Off-state leakage current I
OZ
-1 – 1 µA
High-level output voltage V
OH
I
OH
=-3mA, V
DD
=Min.
V
DD
-0.4
– – V
Low-level output voltage V
OL
I
OL
=3mA, V
DD
=Min. – – 0.4 V
High-level input voltage V
IH
CMOS level, V
DD
=Max. 3.5 – – V
Low-level input voltage V
IL
CMOS level, V
DD
=Min. – – 1.0 V
Positive trigger input voltage V
T+
CMOS schmitt 2.0 – 4.0 V
Negative trigger input voltage V
T-
CMOS schmitt 0.8 – 3.1 V
Hysteresis voltage V
H
CMOS schmitt 0.3 – – V
Pull-up resistor R
PU
V
I
=0V 60 120 288 KΩ
Pull-down registor R
PD
V
I
= V
DD
(#ICEMD) 30 60 144 KΩ
Input pin capacitance C
I
f=1MHz, V
DD
=0V – – 10 pF
Output pin capacitance C
O
f=1MHz, V
DD
=0V – – 10 pF
I/O pin capacitance C
IO
f=1MHz, V
DD
=0V – – 10 pF
Item Symbol Condition Min. Typ. Max. Unit
*
Input leakage current I
LI
-1 – 1 µA
Off-state leakage current I
OZ
-1 – 1 µA
High-level output voltage V
OH
I
OH
=-2mA, V
DD
=Min.
V
DD
-0.4
– – V
Low-level output voltage V
OL
I
OL
=2mA , V
DD
=Min. – – 0.4 V
High-level input voltage V
IH
CMOS level, V
DD
=Max. 2.4 – – V
Low-level input voltage V
IL
CMOS level, V
DD
=Min. – – 0.4 V
Positive trigger input voltage V
T+
LVTTL schmitt 1.1 – 2.4 V
Negative trigger input volt-
age
V
T-
LVTTL schmitt 0.6 – 1.8 V
Hysteresis voltage V
H
LVTTL schmitt 0.1 – – V
Pull-up resistor R
PU
V
I
=0V
Other than DSIO 80 200 480 kΩ
DSIO 40 100 240 kΩ
Pull-down registor R
PD
V
I
=V
DD
(#ICEMD) 40 100 240 kΩ
Input pin capacitance C
I
f=1MHz, V
DD
=0V – – 10 pF
Output pin capacitance C
O
f=1MHz, V
DD
=0V – – 10 pF
I/O pin capacitance C
IO
f=1MHz, V
DD
=0V – – 10 pF