Specifications

2 C33 Macro Specifications
16
EPSON
S1C33 ASIC DESIGN GUIDE
EMBEDDED ARRAY S1X50000 SERIES
The U_RST_X signal outputs the value of the P_RESETX pad pin shown in the figure.
Figure 2.2 On-Chip User Circuit Clock and Reset Signals
Table 2.5 Clock Operating Modes
(*) Debug mode is the mode used when debugging with the S5U1C33000H.
Halt mode Halt 2 mode SLP mode Debug mode*
U_PERICLK RUN RUN STOP STOP
U_BCUCLK RUN STOP STOP RUN
C33 MACRO
P_OSC1
P_OSC3
OSC1
PLL
CLG
CLOCK TREE
CLOCK TREE
CLOCK TREE
OSC3
CPU
BCU
U_PLLCLK
U_OSC1CLK
U_OSC3CLK
PERIPHERAL
P_X2SPD
P_RESETX
U_PERICLK
U_BCUCLK
U_BCLK
U_RST_X