Specifications

2 C33 Macro Specifications
S1C33 ASIC DESIGN GUIDE
EPSON
15
EMBEDDED ARRAY S1X50000 SERIES
2.4 Special Signals
The U_BUSSZ[1:0] and U_BUSMD[2:0] signals indicate the state of the bus cycle currently
executing on the chip external bus and the internal bus (the internal bus including the on-chip user
logic). First, when U_BUSSZ[1:0] is 11, the bus is in the idle state, and the U_BUSMD[2:0] signals
have no meaning. This indicates that the neither the CPU nor the DMA controller is executing a
meaningful bus cycle. When U_BUSSZ[1:0] is not 11, U_BUSSZ[1:0] itself indicates the bus
operation data cycle at that point and U_BUSMD[2:0] indicates the bus state.
2.5 Clock and Reset Signals
There are 6 clock signals that can be connected to the user logic as follows.
U_PLLCLK, U_OSC1CLK, U_OSC3CLK, U_BCLK, U_BCUCLK, U_PERICLK
Figure 2.2 presents an overview of the clock and reset signals. U_OSC3CLK is the output from the
high-speed oscillator circuit (OSC3), and U_PLLCLK is the output from the PLL circuit. This means
that the frequency of the U_PLLCLK signal is determined by the inputs to pin P_PLLS1 and
P_PLLS0. For example, if the OSC3 oscillator frequency is 20 MHz, P_PLLS1 is 1, and P_PLLS0 is
0, then these clocks will have the following frequencies.
U_PLLCLK=40MHz,
U_OSC3CLK=20MHz
Note that the phases of these clocks do not match the phases of the CPU and BCU internal clocks due
to clock tree synthesis. Since both U_OSC3CLK and U_PLLCLK are generated from the OSC3 clock,
they will stop when the CPU executes a SLP instruction until sleep mode is cleared. Furthermore,
when the OSC3 oscillator starts operating again due to the factor that cleared sleep mode, the
U_OSC3CLK and U_PLLCLK signals will be unstable for a certain period, normally about 10 ms.
U_OSC1CLK is the output from the low-speed oscillator circuit.
U_BCUCLK and U_PERICLK are clocks to which the same clock tree synthesis applied as that for
the clocks used by the C33 core.
U_BCLK is the bus clock output from the BCU. Refer to the description of the bus clocks in the
"S1C33 Family ASIC Macro Manual" for more information on the bus clocks.
Table 2.4 Bus Cycle States
U_BUSMD[2:0] 000
001
010
011
100
101
110
111
CPU instruction fetch cycle
CPU vector fetch cycle
CPU data read cycle
CPU data write cycle
CPU stack read cycle
CPU stack write cycle
DMA data read cycle
DMA data write cycle
U_BUSSZ
[1:0] 00
01
10
11
Byte (8 bits)
Half word (16 bits)
Word (32 bits)
Idle state