Specifications

2 C33 Macro Specifications

EPSON

S1C33 ASIC DESIGN GUIDE

EMBEDDED ARRAY S1X50000 SERIES

Table 2.3.5 User Logic Interface Pins

Connection: User logic

Pin I/O Cell name (fanout) Function

U_ADDR[23:0] O XBF4 Address bus

U_DOUT[15:0] O XBF4 Output data bus

U_DIN[15:0] I XAO22V Input data bus

U_CE10_X O XBF4 User logic chip enable

U_CE9_X O XBF4 User logic chip enable

U_CE8_X O XBF4 User logic chip enable

U_CE7_X O XBF4 User logic chip enable

U_CE6_X O XBF4 User logic chip enable

U_CE5_X O XBF4 User logic chip enable

U_CE4_X O XBF4 User logic chip enable

U_WRL_X O XBF4 Lower byte write strobe

U_WRH_X O XBF4 Upper byte write strobe

U_RD_X O XBF4 Read strobe

U_WAIT_X I XAO22V Wait signal

U_P3_PIN[5:0] O XBF2 P3 port input value (Separated test input)

U_P2_PIN[7:0] O XBF2 P2 port input value (Separated test input)

U_P1_PIN[6:0] O XBF2 P1 port input value (Separated test input)

U_P0_PIN[7:0] O XBF2 P0 port input value (Separated test input)

U_K5_PIN[4:0] O XBF2 K5 port input value (Separated test input)

U_BUSMD[2:0] O XBF2 Bus cycle status signal

U_BUSSZ[1:0] O XBF2 Bus size signal

U_BCLK O XBF4 Bus clock

U_OSC1CLK O XBF4 Low-speed oscillator circuit output

U_OSC3CLK O XBF4 High-speed oscillator circuit output

U_PLLCLK O XBF4 PLL circuit output

U_BCUCLK O XCRBF6 BCU clock (CTS support)

U_PERICLK O XCRBF6 Peripheral circuit clock (CTS support)

U_RST_X O XBF4 Reset signal

TST_USER O XBF2 User circuit test mode

TST_TA O XBF16 I/O cell TA pin connection signal

TST_TE_X O XBF16 I/O cell TE pin connection signal

TST_TS O XBF16 I/O cell TS pin connection signal