Specifications

2 C33 Macro Specifications

S1C33 ASIC DESIGN GUIDE

EPSON

EMBEDDED ARRAY S1X50000 SERIES

(*) Pins P_P10 to P_P14 are used as S5U1C33000H interface pins.

(**) Analog input and digital input shared function input buffer

The customer can select whether or not each of the above optional pins is connected to a pad. If the

pin is not connected to a pad, it can be used as an internal signal with the same meaning. In that case,

the fan-in and fan-out values are equivalent to those for XBF2 from the S1X50000 Series library.

(4) C33 Macro - User logic interface pins (chip internal connections)

When the corresponding area is in on-chip mode due to BCU register settings, the following signals

and bus lines will be active when the bus is operational.

The C33 memory area is divided into 19 areas (area 0 through area 18). Basically, areas 4 to 18 are

external (off-chip) memory areas, and areas 0 to 3 are internal (on-chip) memory areas. The operating

conditions for these areas, such as type of memory used (SRAM, ROM, RAM, DRAM), device size

(8-bit or 16-bit data width), and timing (wait cycles and output disable cycles) are set using the BCU

registers. Additionally, it is also possible, using other BCU registers, to set up specific areas in areas

4 to 18 as external areas on the external bus and to have the other areas function as internal areas on

the internal bus as described later in this section.

Even in cases where specific areas as set up as on-chip (i.e. on the internal bus) areas, the operating

conditions for those areas, such as type of memory used (SRAM, ROM, RAM, DRAM), device size

(8-bit or 16-bit data width), and timing (wait cycles and output disable cycles), can be set in the same

way with the BCU registers.

Name I/O Cell name Pull-u/d Function

P_P07 I/O XHBH1T

I/O shared function port. When /CFP07(D7/0x402D0) and

CFEx7(D7/0x402DF) = 0 (default)

P_P06 I/O XHBH1T

I/O shared function port. When /CFP06(D6/0x402D0) and

CFEx6(D6/0x402DF) = 0 (default)

P_P05 I/O XHBH1T

I/O shared function port. When /CFP05(D5/0x402D0) and

CFEx5(D5/0x402DF) = 0 (default)

P_P04 I/O XHBH1T

I/O shared function port. When /CFP04(D4/0x402D4) and

CFEx4(D4/0x402LDF) = 0 (default)

P_P03 I/O XHBH1T I/O shared function port. When /CFP03(D3/0x402DC) = 0 (default)

P_P02 I/O XHBH1T I/O shared function port. When /CFP02(D2/0x402DC) = 0 (default)

P_P01 I/O XHBH1T I/O shared function port. When /CFP01(D1/0x402DC) = 0 (default)

P_P00 I/O XHBH1T I/O shared function port. When /CFP00(D0/0x402DC) = 0 (default)

P_OSC2 O XLLOT Low-speed oscillator (OSC1) output

P_OSC1 I XLLIN

Low-speed oscillator (OSC1) input (32 kHz oscillator

element connection or external clock input)

Connection: PAD_PERI