Specifications

2 C33 Macro Specifications

S1C33 ASIC DESIGN GUIDE

EPSON

EMBEDDED ARRAY S1X50000 SERIES

(2) C33 Macro - Optional pins (pad connections) (12 pins)

Table 2.3.2 Optional Pins

Connection: PAD_CORE_OPTION

(*) Pins P_CE4_X to P_CE9_X function as output pins due to test circuit modifications.

The customer can select whether or not each of the above optional pins is connected to a pad. If the

pin is not connected to a pad, it can be used as an internal signal with the same meaning. In that case,

the fan-in and fan-out values are equivalent to those for XBF2 from the S1X50000 library.

Table 2.3.3 P_EA10M2, P_EA10M1, and P_EA10M0 Settings

(Area 10 Boot Mode) Function

Name I/O Cell name Pull-u/d Function

P_LCAS_X O XHTB1T DRAM lower byte CAS signal

P_HCAS_X O XHTB1T DRAM upper byte CAS signal

P_CE10IN O XHTB1T Internal ROM emulation area (area 10) chip enable

P_CE9_X I/O XHBC1T Chip enable (area 9 or area 17)

P_CE8_X I/O XHBC1T

Chip enable (area 8 or area 14) or the area 8 and 14

DRAM strobe

P_CE7_X I/O XHBC1T

Chip enable (area 7 or area 13) or the area 7 and 13

DRAM strobe

P_CE6_X I/O XHBC1T Chip enable (area 6)

P_CE5_X I/O XHBC1T Chip enable (area 5 or area 15)

P_CE4_X I/O XHBC1T Chip enable (area 4 or area 11)

P_CE3_X O XHTB1T Chip enable (area 3)

P_EMEMRD O XHTB1T Internal ROM emulation area (area 10) read strobe

P_EA10M2 I XHIBC Area 10 boot mode specification bit 2

P_EA10M2 P_EA10M1 P_EA10M0 Function

0 0 0 Internal ROM emulation

0 0 1 Reserved

010 Internal ROM

011 External ROM

1 0 0 Reserved

1 0 1 Reserved

1 1 0 Reserved

1 1 1 Internal flash ROM