Specifications

2 C33 Macro Specifications
10
EPSON
S1C33 ASIC DESIGN GUIDE
EMBEDDED ARRAY S1X50000 SERIES
2.3 C33 Macro Pins
(1) C33 Macro - Required pins (pad connections)
(2) C33 Macro - Optional pins (pad connections)
(3) C33 Macro - Peripheral function pins (pad connections)
(4) C33 Macro - User pins (chip internal connections)
(1) C33 Macro - Required pins (pad connections) (57 pins)
These required pins must be connected to IC package pins.
Table 2.3.1 Required Pins
Connection: PAD_CORE
(*) Functions as an input in test mode.
(**) Refer to table 2.3.3 for the setting values.
(***) P_PLLS[1:0] pin settings
00: PLL unused. (The OSC3 input is used as the system clock.)
01: 4 × mode. fin = 10 to 15 MHz, fout = 40 to 60 MHz
11: 2 × mode. fin = 10 to 30 MHz, fout = 20 to 60 MHz
(****) The type can be modified as specified by the customer.
Refer to the "S1L50000 SERIES MSI Cell Library" manual for more information on the cell type.
Name I/O
Cell name
(****)
Pull-u/d Function
P_A23 to P_A0 I/O(*) XHBC1T
24-bit address bus. A0 is shared with the #BSL pin
function.
P_D15 to P_D0 I/O XHBC1T 16-bit data bus
P_CE10EX I/O(*) XHBC1T Area 10 chip enable/test clock
P_RD_X I/O(*) XHBC1T Read strobe
P_WRL_X I/O(*) XHBC1T Lower byte write strobe
P_WRH_X I/O(*) XHBC1T Upper byte write strobe
P_BCLK O XHTB1T Bus clock
P_NMI_X I XHIBHP2 Pull-up Nonmaskable interrupt
P_RESETX I XHIBHP2 Pull-up Reset signal
P_X2SPDX I XHIBC
Double-speed mode (The CPU clock operates at a
frequency twice that of the bus clock.)
P_TST I XITST1 Pull-down Test mode
P_EA10M1 I XHIBHP2 Pull-up Area 10 boot mode specification bit 1 (**)
P_EA10M0 I XHIBC Area 10 boot mode specification bit 0 (**)
P_DSIO I/O XLBH2P2T Pull-up On-chip ICE serial I/O
P_OSC4 O XLLOT High-speed oscillator output
P_OSC3 I XLLIN
High-speed oscillator input (oscillator element con-
nection)
P_PLLS1 I XHIBC PLL mode specification bit 1 (***)
P_PLLS0 I XHIBC PLL mode specification bit 0 (***)
P_PLLC O XLLIN PLL capacitor connection