Specifications

2 C33 Macro Specifications
8
EPSON
S1C33 ASIC DESIGN GUIDE
EMBEDDED ARRAY S1X50000 SERIES
2.2 Block Diagram
Figure 2.1 C33 Macro Block Diagram
Terminology
BCU: Bus control unit
ITC: Interrupt controller
CLG: Clock generator (oscillator circuit, PLL, and clock divider circuits built in)
DBG: Debugging function block (On-chip ICE)
C33_CORE: Functional blocks such as CPU, BCU, ITC, CLG, and DBG blocks
PAD_CORE: I/O pad block for C33_CORE blocks
PAD_
CORE_
OPTION
DMA
(1) Required pins
(4) User pins
Internal RAM
(area 0)
Internal ROM
(area 10)
C33_CORE
PAD_
CORE
PAD_
PERI
(3) Peripheral
function pins
SBUS
C33 CORE BLOCK
User logic
interface
User logic
(CPU,BCU,ITC,CLG,DBG)
C33_PERI
(PSC,T8,T16,SIO,PORT)
ADC
(2) Optional pins