Specifications

2 C33 Macro Specifications

S1C33 ASIC DESIGN GUIDE

EPSON

EMBEDDED ARRAY S1X50000 SERIES

Chapter 2 C33 Macro Specifications

2.1 Overview

The C33 macro model has the structure described below. Seiko Epson provides a combination of these

elements as specified by user options.

! C33_CORE

• C33 core macros

• CPU, BCU (bus control unit), ITC (Interrupt controller), DBG (debugging unit), and high-

speed oscillator circuit (including PLL circuit) macros

• About 60,000 gates

• Hard macro

! C33_PERI

• C33 digital peripheral function macros

• 4-channel 8-bit timer, 6-channel 16-bit timer, prescaler, 2-channel serial interface, watchdog

timer, clock timer, low-speed oscillator circuit (32 kHz), and I/O port macros

• About 20,000 gates

• Soft macros

! C33_AD

• C33 analog peripheral function macros

• 8-channel input and 10-bit successive-approximation converters

• Conversion time: 10 µs

• About 10,000 gates

• Hard macros

! C33_DMA

• C33 DMA function macros

• 4-channel high-speed DMA and 128-channel intelligent DMA macros

• About 10,000 gates

• Hard macros

(*)

• Soft macro: Net list or RTL macro for which the layout is not fixed.

• Hard macro: Net list macro for which the layout is fixed.