Specifications

1 Product Overview
S1C33 ASIC DESIGN GUIDE
EPSON
5
EMBEDDED ARRAY S1X50000 SERIES
Figure 1.2 Division of Responsibility in the Development Process
(Development Flowchart Organized by Responsibility)
Continued on following page.
User Responsibility Seiko Epson Responsibility
Specification request
Verification of CPU and chip specifications
Investigation
Library creation
Approval to start development
Bulk signoff
Provision of a design kit
User logic design
Pre-simulation
P&R
Post-simulation
Internal ROM program creation
Inspection and verification
Metal signoff
Mask creation
Library
C33 design kit
S1X50000 Series design kit
Floorplan
Preliminary P&R
User logic design
Pre-simulation
Net list
Test patterns (apf)
User logic design
Post-simulation
Simulation
results
Logic specifications
confirmation verification document
sdf
Pin arrangement table
Provisional net list
Development
specifications
document
ROM data
User Responsibility Seiko Epson Responsibility
Specification request
Verification of CPU and chip specifications
Investigation
Library creation
Approval to start development
Bulk signoff
Provision of a design kit
User logic design
Pre-simulation
P&R
Post-simulation
Internal ROM program creation
Inspection and verification
Metal signoff
Mask creation
Library
C33 design kit
S1X50000 Series design kit
Floorplan
Preliminary P&R
User logic design
Pre-simulation
Net list
Test patterns (apf)
User logic design
Post-simulation
Simulation
results
Logic specifications
confirmation verification document
sdf
Pin arrangement table
Provisional net list
Development
specifications
document
ROM data