Specifications

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MF1359-02

ASIC DESIGN GUIDE

CMOS 32

BIT SINGLE CHIP MICROCOMPUTER

Embedded Array S1X50000 Series

S1C33

Summary of content (98 pages)

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MF1359-02 CMOS 32-BIT SINGLE CHIP MICROCOMPUTER S1C33 ASIC DESIGN GUIDE Embedded Array S1X50000 Series
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NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
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The information of the product number change Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative.
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Contents Contents Chapter 1 Product Overview ................................................................ 1 1.1 Introduction ........................................................................... 1 1.2 Interface and Design Process Flowchart .............................. 3 Chapter 2 C33 Macro Specifications .................................................... 7 2.1 2.2 2.3 2.4 2.5 2.6 Overview ............................................................................... 7 Block Diagram ........
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Contents Chapter 4 Special Operations in ASICs that Include C33 Macros ...... 62 4.1 Special Operations ............................................................. 62 4.2 Verifying the C33 Macro Specifications .............................. 62 4.3 Verifying the Constraints on the Pin Arrangement ............. 63 4.3.1 Constraints on PLL, Low-speed, and High-speed Oscillator Circuit Pins ................................................................................. 63 4.3.
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1 Product Overview Chapter 1 Product Overview 1.1 Introduction This product, abbreviated here as "C33," is an ASIC macro family that consists of Seiko Epson's independently developed S1C33000 Series 32-bit CPU core and macros for a wide range of peripheral functions. The C33 macros can be integrated on Seiko Epson's 0.35 µm embedded ASIC family (S1X50000 Series) ICs. SRAM, ROM, and flash memory ASIC memory macros that share the same process technology can be integrated on the same chip.
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1 Product Overview • Other features: Little endian (Certain areas can be set up for big endian operation.) *: In addition to this documents, you will also find the following documents of use when designing ASICs.
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1 Product Overview 1.
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1 Product Overview Table 1.
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1 Product Overview User Responsibility Seiko Epson Responsibility Investigation Specification request Verification of CPU and chip specifications Approval to start development Library creation Provision of a design kit Library User logic design Pin arrangement table Provisional net list Development specifications document C33 design kit S1X50000 Series design kit Floorplan Preliminary P&R Bulk signoff User logic design Pre-simulation Net list Test patterns (apf) Pre-simulation P&R User logic desi
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1 Product Overview User Responsibility Seiko Epson Responsibility TS (test sample) production Functional evaluation ES (engineering sample) production Overall evaluation Qualification of mass production ES approval 6 EPSON S1C33 ASIC DESIGN GUIDE EMBEDDED ARRAY S1X50000 SERIES
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2 C33 Macro Specifications Chapter 2 C33 Macro Specifications 2.1 Overview The C33 macro model has the structure described below. Seiko Epson provides a combination of these elements as specified by user options.
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2 C33 Macro Specifications 2.2 Block Diagram DMA Internal RAM (area 0) Internal ROM (area 10) C33_CORE PAD_ CORE (1) Required pins PAD_ CORE_ OPTION (2) Optional pins (CPU,BCU,ITC,CLG,DBG) (4) User pins SBUS User logic interface C33 CORE BLOCK C33_PERI User logic (PSC,T8,T16,SIO,PORT) PAD_ PERI (3) Peripheral function pins ADC Figure 2.
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2 C33 Macro Specifications SBUS: Bus control block that has an address/data bus structure connected to the user logic. C33_PERI: C33 peripheral function blocks. These blocks include prescaler, 8-bit timer (4 channels), 16-bit timer (6 channels), serial interface (2 channels), port (input, output, and I/O), and clock timer blocks.
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2 C33 Macro Specifications 2.3 (1) (2) (3) (4) C33 Macro Pins C33 Macro - Required pins (pad connections) C33 Macro - Optional pins (pad connections) C33 Macro - Peripheral function pins (pad connections) C33 Macro - User pins (chip internal connections) (1) C33 Macro - Required pins (pad connections) (57 pins) These required pins must be connected to IC package pins. Table 2.3.1 Required Pins Connection: PAD_CORE Cell name (****) Name I/O P_A23 to P_A0 I/O(*) XHBC1T 24-bit address bus.
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2 C33 Macro Specifications (2) C33 Macro - Optional pins (pad connections) (12 pins) Table 2.3.
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2 C33 Macro Specifications (3) C33 Macro - Peripheral function pins (pad connections) (44 pins) Table 2.3.4 Peripheral Function Pins Connection: PAD_PERI Name P_K67 P_K66 P_K65 P_K64 P_K63 P_K62 P_K61 P_K60 I/O I I I I I I I I P_K54 P_K53 P_K52 P_K51 P_k50 I I I I I XHIBHP2 XHIBHP2 XHIBHP2 XHIBHP2 XHIBHP2 P_P35 P_P34 P_P33 P_P32 P_P31 P_P30 I/O I/O I/O I/O I/O I/O XHBH1T XHBH1T XHBH1T XHBH1T XHBH1T XHBH1T I/O shared function port. When /CFP35(D5/0x402DC) = 0 (default) I/O shared function port.
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2 C33 Macro Specifications Connection: PAD_PERI Name I/O Cell name P_P07 I/O XHBH1T P_P06 I/O XHBH1T P_P05 I/O XHBH1T P_P04 I/O XHBH1T P_P03 P_P02 P_P01 P_P00 I/O I/O I/O I/O XHBH1T XHBH1T XHBH1T XHBH1T P_OSC2 O XLLOT P_OSC1 I XLLIN (*) (**) Pull-u/d Function I/O shared function port. When /CFP07(D7/0x402D0) and CFEx7(D7/0x402DF) = 0 (default) I/O shared function port. When /CFP06(D6/0x402D0) and CFEx6(D6/0x402DF) = 0 (default) I/O shared function port.
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2 C33 Macro Specifications Table 2.3.
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2 C33 Macro Specifications 2.4 Special Signals The U_BUSSZ[1:0] and U_BUSMD[2:0] signals indicate the state of the bus cycle currently executing on the chip external bus and the internal bus (the internal bus including the on-chip user logic). First, when U_BUSSZ[1:0] is 11, the bus is in the idle state, and the U_BUSMD[2:0] signals have no meaning. This indicates that the neither the CPU nor the DMA controller is executing a meaningful bus cycle.
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2 C33 Macro Specifications The U_RST_X signal outputs the value of the P_RESETX pad pin shown in the figure. C33 MACRO PLL U_PLLCLK P_OSC1 OSC1 U_OSC1CLK P_OSC3 OSC3 U_OSC3CLK CLG CPU CLOCK TREE PERIPHERAL CLOCK TREE U_PERICLK CLOCK TREE U_BCUCLK BCU P_X2SPD U_BCLK P_RESETX U_RST_X Figure 2.2 On-Chip User Circuit Clock and Reset Signals Table 2.
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2 C33 Macro Specifications 2.6 Electrical Characteristics The C33 macro I/O cell library is designed based on the S1L50000 Series. Therefore, the electrical characteristics are basically the same as those of the S1L50000 Series. However, since the C33 macros include function blocks, such as CPU, DMA, PLL, oscillator, and A/D converter blocks, that have unique and special characteristics, this manual stipulates the electrical characteristics for this product.
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2 C33 Macro Specifications 2.6.2 Recommended Operating Conditions 1) 3.3V single power source (VSS=0V) Item Supply voltage Input voltage Symbol Condition VDD Min. Typ. Max. Unit 3.00 3.30 3.60 V 2.70 3.00 3.30 V V VSS – VDD*1 ROM-less model and 3.0±0.3V – – 60 MHz ROM model and 3.0±0.3V – – 50 MHz – 32.
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2 C33 Macro Specifications 3) 3.3 V/5.0 V dual power source (VSS=0V) Item Symbol Min. Typ. Max. Unit 4.75 5.00 5.25 V 4.50 5.00 5.50 V 3.00 3.30 3.60 V 2.70 3.00 3.30 V HVI VSS – HVDD V LVI VSS – VSS – ROM-less model and 3.0±0.3V – – 60 MHz ROM model and 3.0±0.3V – – 50 MHz – 32.
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2 C33 Macro Specifications 2.6.3 DC Characteristics 1) 3.3V/5.0V dual power source (Unless otherwise specified: HVDD=4.5V to 5.5V, LVDD=2.7V to 3.6V, VSS=0V, Ta=–40 to +85°C) Item Symbol Min. Typ. Max. Unit -1 – 1 µA IOZ -1 – 1 µA High-level output voltage VOH IOH=-3mA, VDD=Min. VDD -0.4 – – V Low-level output voltage VOL IOL=3mA, VDD=Min. – – 0.4 V High-level input voltage VIH CMOS level, VDD=Max. 3.5 – – V Low-level input voltage VIL CMOS level, VDD=Min. – – 1.
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2 C33 Macro Specifications 3) 2.0V single power source (Unless otherwise specified: VDD=1.8V to 2.2V, VSS=0V, Ta=–40 to +85°C) Item Symbol Condition Min. Typ. Max. Unit Input leakage current ILI -1 – 1 µA Off-state leakage current IOZ -1 – 1 µA High-level output voltage VOH IOH=-0.6mA, VDD=Min. VDD-0.2 – – V Low-level output voltage VOL IOL=0.6mA, VDD=Min. – – 0.2 V High-level input voltage VIH CMO level, VDD=Max. 1.
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2 C33 Macro Specifications 2) 2.0V single power source (Unless otherwise specified: VDD=1.8V to 2.2V, VSS=0V, Ta=–40 to +85°C) Item Symbol Condition Min. Typ. Max. Unit Operating current IDD1 When CPU is operating 20MHz – 13 19 mA Operating current IDD2 HALT mode 20MHz – 6 9 mA Operating current IDD3 HALT2 mode, 20MHz 20MHz – 0.4 1.
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2 C33 Macro Specifications 2) 3.3V single power source (Unless otherwise specified: VDD=AVDD=2.7V to 3.6V, VSS=AVSS=0V, Ta=0 to +70°C, A/D converter clock input f=2MHz, ST[1:0]=11) Item Symbol Min. Typ. Max.
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2 C33 Macro Specifications ■ Integral linearity error 3FF Digital output (hex) 3FE V'[3FF]h 3FD Integral linearity error EL = VN' - VN [LSB] 1LSB' VN VN' 003 Actual conversion characteristic 002 Ideal conversion characteristic 001 V'[000]h 000 VSS Analog input AVDD ■ Differential linearity error Digital output (hex) N+1 Ideal conversion characteristic N Actual conversion characteristic N-1 V'[N]h Differential linearity error ED = N-2 V'[N-1]h V'[N]h - V'[N-1]h - 1 [LSB] 1LSB' Analog input 2
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2 C33 Macro Specifications 2.6.6.
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2 C33 Macro Specifications 2.6.6.2 AC Characteristics Measurement Condition Signal detection level: Input signal High level VIH = VDD - 0.4 V Low level VIL = 0.
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2 C33 Macro Specifications 2.6.6.3 AC Characteristics Tables (I/O Buffer Pins) The tables in this section stipulate the timing of the interface between the C33 macros and circuits external to the chip. External clock input characteristics Note: These AC characteristics apply to input signals from outside the IC. 1) 3.3V/5.0V dual power source (Unless otherwise specified: HVDD=4.5V to 5.5V, LVDD=2.7V to 3.6V, VSS=0V, Ta=–40 to 85°C) Item Symbol Min.
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2 C33 Macro Specifications BCLK clock output chracteristics Note: These AC characteristic values are applied only when the high-speed oscillation circuit is used. 1) 3.3V/5.0V dual power source (Unless otherwise specified: HVDD=4.5V to 5.5V, LVDD=2.7V to 3.6V, VSS=0V, Ta=–40 to 85°C) Item P_BCLK clock output duty Symbol tCBD Min. Max. Unit 40 60 % * 2) 3.3V single power source (Unless otherwise specified: VDD=2.7V to 3.
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2 C33 Macro Specifications 2) 3.3V single power source (Unless otherwise specified: VDD=2.7V to 3.6V, VSS=0V, Ta=–40 to 85°C) Item Symbol Min. Max.
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2 C33 Macro Specifications 2) 3.3V single power source (Unless otherwise specified: VDD=2.7V to 3.6V, VSS=0V, Ta=–40 to 85°C) Item Symbol Min. Max. Unit 10 ns Read signal delay time (2) tRDD2 Read signal pulse width tRDW Read address access time (1) tACC1 tCYC(1+WC)-25 ns Chip enable access time (1) tCEAC1 tCYC(1+WC)-25 ns Read signal access time (1) tRDAC1 tCYC(0.5+WC)-25 ns tCYC(0.5+WC)-10 * ns 3) 2.0V single power source (Unless otherwise specified: VDD=1.8V to 2.
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2 C33 Macro Specifications DRAM access cycle common characteristics The #RAS and #CAS symbols in the stipulations for the DRAM interface in the following tables are to be interpreted as follows. • #RAS refers to that signal any one of the chip enable signals (P_CEX signals) set up by the bus controller (BCU) to operate as a RAS signal for the DRAM. • #CAS refers to the P_HCAS_X or the P_LCAS_X signal. 1) 3.3V/5.0V dual power source (Unless otherwise specified: HVDD=4.5V to 5.5V, LVDD=2.7V to 3.
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2 C33 Macro Specifications 3) 2.0V single power source (Unless otherwise specified: VDD=1.8V to 2.2V, VSS=0V, Ta=–40 to 85°C) Item Symbol Min. Max.
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2 C33 Macro Specifications EDO DRAM random access cycle and EDO DRAM page cycle 1) 3.3V/5.0V dual power source (Unless otherwise specified: HVDD=4.5V to 5.5V, LVDD=2.7V to 3.6V, VSS=0V, Ta=–40 to 85°C) Item Symbol Min. Max. Unit Column address access time tACCE tCYC(1.5+WC)-25 ns #RAS access time tRACE tCYC(2+WC)-25 ns #CAS access time tCACE tCYC(1+WC)-15 ns Read data setup time tRDS2 20 * ns 2) 3.3V single power source (Unless otherwise specified: VDD=2.7V to 3.
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2 C33 Macro Specifications Burst ROM read cycle 1) 3.3V/5.0V dual power source (Unless otherwise specified: HVDD=4.5V to 5.5V, LVDD=2.7V to 3.6V, VSS=0V, Ta=–40 to 85°C) Item Symbol Min. Max. Unit Read address access time (2) tACC2 tCYC(1+WC)-20 ns Chip enable access time (2) tCEAC2 tCYC(1+WC)-20 ns Read signal access time (2) tRDAC2 tCYC(0.5+WC)-20 ns Burst address access time tACCB tCYC(1+WC)-20 ns * 2) 3.3V single power source (Unless otherwise specified: VDD=2.7V to 3.
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2 C33 Macro Specifications 1) 3.3V/5.0V dual power source (Unless otherwise specified: HVDD=4.5V to 5.5V, LVDD=2.7V to 3.6V, VSS=0V, Ta=–40 to 85°C) Item Symbol Min. Max. Unit #BUSREQ signal setup time tBRQS 15 ns #BUSREQ signal hold time tBRQH 0 ns #BUSACK signal output delay time tBAKD 10 ns High-impedance → output delay time tZ2E 10 ns Output → high-impedance delay time tB2Z 10 ns #NMI pulse width tNMIW 30 * ns 2) 3.3V single power source (Unless otherwise specified: VDD=2.
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2 C33 Macro Specifications Input, Output and I/O port The tables in this section stipulate the AC characteristics of the P_Pxx and P_Kxx ports. 1) 3.3V/5.0V single power source (Unless otherwise specified: HVDD=4.5V to 5.5V, LVDD=2.7V to 3.6V, VSS=0V, Ta=–40 to 85°C) Item Symbol Min. Input data setup time tINPS 20 Input data hold time tINPH 10 Output data delay time tOUTD P_Kxx-port interrupt SLEEP, HALT2 mode input pulse width Others tKINW Max.
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2 C33 Macro Specifications 2.6.6.4 AC Characteristics Timing Charts (I/O Buffer Pins) This section presents the timing charts for the interface between the C33 macros and chip-external circuits.
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2 C33 Macro Specifications SRAM read cycle (when a wait cycle is inserted) C1 Cw (wait cycle) Cn (last cycle) P_BCLK tAD tAD tCE1 tCE2 P_A[23:0] P_CEx tRDD1 (C1 only) tRDD2 tRDW P_RD_X tCEAC1 tACC1 tRDAC1 P_D[15:0] tWTS tWTH tWTS tWTH tRDS tRDH *1 P_P30 (Wait input) ∗1 tRDH is measured with respect to the first signal change (negation) from among the P_RD, P_CEx, or the P_A[23:0] signals.
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2 C33 Macro Specifications SRAM write cycle (when wait cycles are inserted) C1 Cw (wait cycle) Cw (wait cycle) Wait cycle follows Last cycle follows Cn (last cycle) P_BCLK tAD tAD tCE1 tCE2 P_A[23:0] P_CEx tWRD1 tWRD2 tWRW P_WRx_X tWDD1 tWDH P_D[15:0] tWTS tWTH tWTS tWTH tWTS tWTH P_P30 (Wait input) DRAM random access cycle (basic cycle) Data transfer #1 RAS1 Next data transfer CAS1 PRE1 (precharge) RAS1' CAS1' P_BCLK tAD tAD tAD P_A[23:0] tRASD1 tRASD2 tRASW P_CEx (RAS
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2 C33 Macro Specifications DRAM fast-page access cycle Data transfer #1 RAS1 Data transfer #2 CAS1 CAS2 Next data transfer PRE1 (precharge) RAS1' P_BCLK tAD tAD tAD P_A[23:0] tRASD1 tRASD2 tRASW P_CEx (RAS output) tCASD1 tCASD2 tCASW P_HCAS_X/ P_LCAS_X tRDD1 tRDD3 tRDW2 P_RD_X tCACF tACCF tRACF tACCF tRDS P_D[15:0] (Read) *1 tRDH tRDS *1 tRDH tWRD1 tWRD3 tWRW2 P_WRL_X tWDD1 tWDD2 tWDD2 P_D[15:0] (Write) ∗1 tRDH is measured with respect to the first signal change (negation)
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2 C33 Macro Specifications EDO DRAM page access cycle Data transfer #1 RAS1 Data transfer #2 CAS1 CAS2 Next data transfer PRE1 (precharge) RAS1' P_BCLK tAD tAD tAD P_A[23:0] tRASD1 tRASD2 tRASW P_CEx (RAS output) tCASD1 tCASD2 tCASW P_HCAS_X/ P_LCAS_X tRDD1 tRDD3 tRDW2 P_RD_X tACCE tCACE tRACE tRDS tRDH tRDS tRDH *1 tACCE P_D[15:0] (Read) tWRD1 tWRD3 tWRW2 P_WRL_X tWDD1 tWDD2 tWDD2 D[15:0] (Write) ∗1 tRDH is measured with respect to the first signal change from among the P_RD
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2 C33 Macro Specifications Burst ROM read cycle SRAM read cycle Burst cycle Burst cycle Burst cycle P_BCLK tAD tAD P_A[23:2] tAD tAD tAD tAD tAD P_A[1:0] tCE1 tCE2 P_CEx tRDD1 tRDD2 P_RD_X tACC2 tCEAC tRDAC2 tRDS tACCB tACCB tRDS tACCB tRDS tRDS P_D[15:0] tRDH tRDH tRDH tRDH*1 ∗1 tRDH is measured with respect to the first signal change (negation) from among the P_RD, P_CEx, or the P_A[23:0] signals.
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2 C33 Macro Specifications 2.6.6.5 AC Characteristics Tables (User Logic Interface) The tables in this section stipulate the timing of the interface between the C33 macros and the user logic on the same chip. (Note that these timing values must be verified by simulation at the end of the development process.) External clock input characteristic This table stipulates the AC characteristics for VDD in the range 3.0 to 3.6 V.
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2 C33 Macro Specifications Common Characteristics (User Logic Interface) The VDD and VSS levels are always used for the interface with user logic. (Unless otherwise specified: VDD=3.0V to 3.6V, VSS=0V, Ta=–40 to 85°C) Item Symbol Min. Max.
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2 C33 Macro Specifications 2.6.6.6 AC Characteristics Timing Charts (User Logic Interface) This section presents the timing charts for the interface between C33 macros and the user logic on the same chip.
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2 C33 Macro Specifications Reset P_RESETX U_BCUCLK tURST tURA tURD U_RST_X SRAM read cycle (Basic cycle: 1 cycle) tC3 U_BCUCLK tAD tAD tCE1 tCE2 U_ADDR[23:0] U_CEx tRDD1 tRDD2 tRDW U_RD_X tCEAC1 tACC1 tRDAC1 U_DIN[15:0] tRDS tWTS tRDH *1 tWTH U_WAIT_X ∗1 tRDH is measured with respect to the first signal change (negation) of either the P_RD, P_CEx, or the P_A[23:0] signals.
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2 C33 Macro Specifications SRAM read cycle (when a wait cycle is inserted) C1 Cw (wait cycle) Cn (last cycle) U_BCUCLK tAD tAD tCE1 tCE2 U_ADDR[23:0] U_CEx tRDD1 (C1 only) tRDD2 tRDW U_RD_X tCEAC1 tACC1 tRDAC1 U_DIN[15:0] tWTS tWTH tWTS tWTH tRDS tRDH *1 U_WAIT_X ∗1 tRDH is measured with respect to the first signal change (negation) of either the P_RD, P_CEx, or the P_A[23:0] signals.
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2 C33 Macro Specifications SRAM write cycle (when wait cycles are inserted) C1 Cw (wait cycle) Cw (wait cycle) Wait cycle follows Last cycle follows Cn (last cycle) U_BCUCLK tAD tAD tCE1 tCE2 U_ADDR[23:0] U_CEx tWRD1 tWRD2 tWRW U_WRL_X/ U_WRH_X tWDD1 tWDH U_DOUT[15:0] tWTS tWTH tWTS tWTH tWTS tWTH U_WAIT_X Input, output and I/O port timing U_BCLK tUINPS U_Kxx, Pxx (input: data read from the port) tUINPH Valid input tUOUTD U_Pxx (output) tUKINW U_Kxx (K-port interrupt input) 4
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2 C33 Macro Specifications 2.6.6.7 Oscillation Characteristics Oscillation characteristics change depending on conditions (board pattern, components used, etc.). Use the following characteristics as reference values. In particular, when a ceramic or crystal oscillator is used, use the oscillator manufacturer recommended values for constants such as capacitance and resistance. OSC1 crystal oscillation (Unless otherwise specified: crystal=C-002RX∗1, 32.
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2 C33 Macro Specifications OSC3 crystal oscillation Note: A "crystal resonator that uses a fundamental" should be used for the OSC3 crystal oscillation circuit. (Unless otherwise specified: VSS=0V, crystal=MA-306∗1, 33.8688MHz, Rf2=1MΩ, CG1=CD1=15pF∗2, Ta=25°C) Item Oscillation start time Symbol tSTA3 Condition Min. Typ. Max. Unit VDD=3.3V 10 ms VDD=2.0V 25 ms * *1 Q22MA306: Crystal resonator made by Seiko Epson *2 "CG1=CD1=15pF" includes board capacitance.
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2 C33 Macro Specifications 2.6.6.8 PLL Characteristics Setting the PLLS0 and PLLS1 pins (recommended operating condition) VDD=2.7V to 3.6V PLL PLLS0 Mode Fin (OSC3 clock) Fout 1 1 ×2 10 to 25MHz 20 to 50MHz 0 1 ×4 10 to 12.5MHz 40 to 50MHz 0 0 PLL not used – – PLLSL PLLS0 Mode Fin (OSC3 clock) Fout 1 1 ×2 10MHz 20MHz 0 0 PLL not used – – VDD=2.0V ± 0.2V PLL characteristics (Unless otherwise specified: VDD =2.7V to 3.6V, VSS=0V, crystal oscillator=SG-8002∗1, R1=4.
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3 C33 Test Functions Chapter 3 C33 Test Functions 3.1 Test Function Overview The C33 macros provide an extensive set of test modes for testing and pre-shipment inspection of the C33 CPU core, I/O, and user circuits. Of these, the following two test modes are provided for use by the user. Note that the test mode is set up by the four pins P_TST, P_RESETX, P_X2SPD, and P_EA10M0, which are C33 macro required pins.
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3 C33 Test Functions 3.2 DC/AC Test Mode (TST_DCT mode) 3.2.1 Procedure to Enter Test Mode Use the following procedure entering test mode. (1) With P_RESETX = 0 and P_TST = 0, input at least 4 clock cycles from P_OSC3 to stabilize the C33 macro internal state. After that, set P_TST to 1. (2) With P_RESETX = 0 and P_TST = 1, input 4 rising edges on the P_X2SPDX signal, which is stable signal in normal mode. (3) Set P_RESETX to 1.
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3 C33 Test Functions 3.2.2 Test Mode In the DC/AC test mode, the user I/O cells are controlled by the C33 macro user pin internal signals, namely the TST_TA, TST_TE_X, and TST_TS signals. Note that when P_TST is high, the I/O pullup/pull-down resistors are set to the inactive state. The control and output pins function as follows in this test mode. Table 3.
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3 C33 Test Functions 3) Input logic level verification mode P_X2SPDX (IP0) ... Fixed at the high level P_EA10M1 (IP1) ... Fixed at either high or low (Either can be selected.) P_EA10M0 (IP2) ... Fixed at the high level Test pins ... High or low level input ... Outputs a high or low level. P_BCLK 4) Special-purpose AC path measurement mode P_X2SPDX (IP0) ... Fixed at the low level P_EA10M1 (IP1) ... Data (high or low level) input P_EA10M0 (IP2) ... Fixed at the high level P_A1 ...
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3 C33 Test Functions $PATTERN # # # # # # # # # # # # PPPPPPPPPPPPPPPPPPPPPPPPBOO ________________________IUU RXIOEEBADDDDDDDDDDDDDDDDOTT E2CSAAC11111119876543210112 SSEC11L 543210 EPM300K TDD MM XX 10 IIIPIIOBBBBBBBBBBBBBBBBBBOO U D U 0 1 2 3 4 5 6 7 8 9 10 11 12 14 15 20 25 30 35 36 40 41 45 46 47 50 52 55 57 60 63 65 68 70 73 75 78 80 85 88 90 93 95 98 100 103 105 56 000P00LXXXXXXXXXXXXXXXXXHLX 000P00LXXXXXXXXXXXXXXXXXHLH 000P00LL0000000000000000HLH 000P00LL0000000000000000HLH 001P00L0000000000000000
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3 C33 Test Functions 108 110 113 115 118 120 123 125 128 130 133 135 140 111P11L000000000000000000ZH 111P11L000000000000000000ZH 111P01L000000000000000000ZH 111P11H000000000000000000ZH 111P01H000000000000000000ZH 111P01H000000000000000000ZH 111P01L000000000000000000ZH 111P01L000000000000000000ZH 111P01H000000000000000000ZH 111P01H000000000000000000ZH 111P01L000000000000000000ZH 111P01L000000000000000000ZH 111P01L000000000000000000ZH Since this example is the result of simulating forcing high/low data on t
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58 Group: A P_OSC3 = X tst_ta = x tst_te_x = x tst_ts = x P_BCLK = x LG = x P_A1 = x P_D%[15:0] = 'h xxxx tst_dct = x P_EA110M0 = 0 P_EA10M1 = 0 P_X2SPDX = 0 P_TST = 0 P_RESETX = 0 DC/AC test mode input sequence x x 0 Cursor1 = 0 ps x Quiescent current drain measurement Bidirectional: input 3-state: high 0000 Quiescent current drain measurement Bidirectional: output 3-state: output FFFF 2,000,000 0000 Output characteristics (VOH/VOL) measurement FFFF 4,000,000 FFFF 6,000,000
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3 C33 Test Functions 3.3 User Circuit Test Mode (TST_USER mode) 3.3.1 Procedure to Enter Test Mode The following presents the procedure entering test mode. (1) With P_RESETX = 0 and P_TST = 0, input at least 4 clock cycles from P_OSC3 to stabilize the C33 macro internal state. After that, set P_TST to 1. After that, system clock input is disabled internally in the C33 macros. (2) With P_RESETX = 0 and P_TST = 1, input 1 rising edge on the P_EA10M0 signal, which is stable signal in normal mode.
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3 C33 Test Functions 3.3.2 Test Mode In user circuit test mode, the clock, address, data, read, write, chip enable, and data bus direction control signals can be controlled from external pins. This allows direct control of user circuits without using C33 CPU operation. The external pins function as follows in this test mode. Table 3.
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3 C33 Test Functions Caution: Provide the chip enable signal to the user circuit as shown below. U_P3_PIN[5:0] U_P2_PIN[7:0] U_P1_PIN[6:0] U_P0_PIN[7:0] U_K5_PIN[4:0] MUX Arbitrary signals U_CEx_X x: 4,5,6,7,8,9 1 To the user circuit 0 S TST_USER Figure 3.
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4 Special Operations in ASICs that Include C33 Macros Chapter 4 Special Operations in ASICs that Include C33 Macros 4.1 Special Operations This chapter describes certain special operations that arise when developing ASICs that include C33 macros in the S1X50000 Series. Refer to the S1L50000 SERIES DESIGN GUIDE for information not provided in this chapter. 4.
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4 Special Operations in ASICs that Include C33 Macros 4.3 Verifying the Constraints on the Pin Arrangement The chip floorplan will differ depending on the chip size and the C33 macro modules selected. The following constraints on the pin arrangement arise due to these variations. Please consult your Seiko Epson ASIC representative when verifying the pin arrangement. 4.3.
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AVDD Separate power supply cell P_K62 P_K61 P_K60 Separate power supply cell 4 Special Operations in ASICs that Include C33 Macros VSS P_PLLC VSS C33_DMA C33_ADC C33_CORE HVDD P_OSC3 P_OSC4 VSS C33_PERI User circuits VSS P_OSC1 P_OSC2 HVDD Figure 4.
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4 Special Operations in ASICs that Include C33 Macros 4.4 Connections between User I/O, User Circuits, and C33 Macros 4.4.1 Connections between C33 Macros and User Circuits The connections between C33 macros and user circuits are handled by connecting the required pins as desired from the C33 macro user pins. Since the user pins can be controlled from external pins in user circuit test mode, there is no need to add special test circuits. 4.4.
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4 Special Operations in ASICs that Include C33 Macros 4.4.4 Connections between C33 Macros and User I/O Figure 4.2 shows examples of connections between C33 macros and user circuits and user I/O.
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4 Special Operations in ASICs that Include C33 Macros 4.5 Test Pattern Creation 4.5.1 DC/AC Test Pattern Creation Of the DC/AC test items, the user must create all the test patterns except the input level verification test. Refer to section 3.2, "DC/AC Test Mode," in this document and the S1L50000 SERIES DESIGN GUIDE for more information on test pattern creation. 4.5.
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5 Simulation Chapter 5 Simulation 5.1 Design Flowchart User circuit development RTL coding Bulk Design Development specification verification Logic synthesis Preliminary Net P&R Logic verification Bulk signoff Logic simulation Metal design Pre-simulation Post-simulation C33 Vector verification Metal signoff Figure 5.
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5 Simulation External memory model (SRAM,DRAM) Verilog netlist C33 MACRO C33 ASM code Test bench creation script C33 Assembler LST2ROM Stimulus ROM code EPSON Lib Test Bench Verilog-XL Trace file Waveform display file Figure 5.2 Simulation Flowchart Table 5.
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5 Simulation 5.2 System Level Simulation CC33 Personal computer Workstation C compiler Assembler Linker Simple assembler C33 custom microcontroller model ROM AS33 RAM An assembler-based evaluation program is loaded into ROM. ASIC and other technologies Verilog simulator Figure 5.3 System Level Simulation 5.3 Test Pattern Creation When the logic design is complete, the next step is test pattern creation.
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5 Simulation 5.4 Simulation Environment 5.4.1 Operating Environment The standard simulation environment that Seiko Epson supports with the C33 product consists of the following. Contact your Seiko Epson representative for details on using other environments. Machine : Sun workstation OS: Solaris 2.5.1 or 2.6 Verilog : Verilog-XL 2.6 or later 5.4.2 Installation Procedure The C33 simulation environment is provided on CD-ROM.
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5 Simulation The C33 macro net list consists of the hard macros, the soft macros, and the I/O cells used. The libraries shown above include a sample that forms the S1C33208, which is a general-purpose model in the C33 Series that uses the C33 macros. Seiko Epson provided hard macros are included in the megacell library. 5.5 Running a Simulation 5.5.1 Preparing for Simulation The following setup is required prior to executing a simulation.
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5 Simulation 5.5.3 Simulation Execution Script The C33 simulation is executed by the following script. $C33/sim/verilog/Sample/t0/verilog.boo $C33/sim/verilog/Sample/t0/qa_sample.csh $C33/sim/verilog/ENV/bin/c33_sim.csh The file verilog.boo is a shell script that sets up the Verilog simulator startup command options and actually starts the Verilog simulator. The file qa_sample.csh is a script that prepares to manage the operations associated with running the simulation using the file c33_sim.csh.
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5 Simulation Example 1) Normal simulation csh> c33_sim.csh sample.asm trc=test1 tcyc=100 cycle=300 tb=abc.tb tb=def.tb The file sample.asm is input and executed at 10 MHz (10 ns) for 300 cycles. The files abc.tb and def.tb are added to the test bench. The output file is ./trc/sample/ test1.trc. A directory with the same name as the ASM_file is created in the trc directory, and the results of the Verilog simulation are stored in a file with the name specified with the trc= option.
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5 Simulation csh> grep //_ _ samplex_f10emux1.tb //_ _.../sim/verilog/ENV/tb/header.tb //_ _.../sim/verilog/ENV/tb/c33_chip.tb //_ _.../sim/verilog/ENV/tb/pll_00.tb //_ _.../sim/verilog/ENV/tb/c33_init.tb //_ _.../sim/verilog/ENV/tb/osc1_5MHz.tb //_ _.../sim/verilog/ENV/tb/mode_x1spd.tb //_ _.../sim/verilog/ENV/tb/ea10md_00.tb //_ _.../sim/verilog/ENV/tb/ea3md_0.tb //_ _.../sim/verilog/ENV/tb/mode_normal.tb //_ _.../sim/verilog/ENV/tb/top1.tb //_ _.../sim/verilog/Sample/t0/tb/cpu_trace.tb ( "...
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5 Simulation 5.6 Evaluation Program Creation 5.6.1 asm33 Assembler Prototype The procedure for using the asm33 assembler prototype and limitations on its use are described below. Other issues follow the contents of the S1C33 Family C Compiler Package Manual. Refer to that manual for more information. (1) Running asm33 After executing $C33/bin/SETUP, enter the following command. csh > asm33 Input file: source file Output lst file: (*.lst) Example: asm33 test.asm This creates the file test.
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5 Simulation (2) Limitations on registers, values, and labels • Character set There are 3 delimiters: space, tab and comma. If the first character is: . ; Pseudoinstruction ; Number 0x[0-9a-fA-F]* a-z,A-Z,_ ; Label or instruction ; Comment ; A single line can hold any one of label definition (label:), instruction, or pseudoinstruction. Only lower case letters may be used in instruction and register names. Both upper and lower case may be used in labels.
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5 Simulation 5) Jump instructions that require an immediate value extended instruction must be coded successively after the extended instruction. (A syntax error results if this is not obeyed.) ext LABEL@rh ext LABEL@rm jp LABEL@rl × ext LABEL@rh ext LABEL@rh [Other instruction] -or- ext LABEL@rm ext LABEL@rm [Other instruction] jp LABEL@rl jpLABEL@rl 6) The maximum number of lines per source file is 65536 lines.
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6 Board Development Chapter 6 Board Development 6.1 Development Environment S5U1C33000C EPSON S5U1C330M1D1 I/F board 33 chip S5U1C330M2S Serial User target board Serial/parallel 4, 10 pins S5U1C33XXXE S5U1C33000H User target board Figure 6.
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6 Board Development • Host computer • Personal computer running Windows 95, 98, or NT • Software tools • S5U1C33000 - Provides tools from a C compiler to a debugger • Hardware and debugging tools • S5U1C33000H (Minimal pin count ICE) - Support for C33 model 2 or later • S5U1C330M2S and S5U1C330M1D1 - Provides a simple debugging environment • S5U1C33XXXE - Adapter board used during ASIC design The following development software is also available. • Real-time OS • S5U1C330R1S - Conforms to the ITRON 3.
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6 Board Development Fast SRAM X 16bit ACC = 15 ns S1C332XX User target board Others Fast SRAM X 8 bit ACC = 15 ns During hardware and software development S1C332XX EPGA or Gate Array SRAM IC With S1C33 macro PAD Pattern Flash Others For mass production Figure 6.
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6 Board Development 6.2 Evaluation Board Design Determination of the C33 ASIC product package specifications EPOD design Target development Evaluation board development Circuit development Circuit development Circuit design OR Manufacturing Manufacturing ES samples Manufacturing Functional verification in an actual end product Issuing as ROM Figure 6.
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6 Board Development (1) Board development process (example 1) Step 1: Determine the C33 ASIC product package and pin arrangement. Step 2: Perform performance and user circuit evaluation by creating a target board (mass production version), and, at the same time, creating an EPOD board with an FPGA by using a C33209 (a general-purpose product). Also, start software development. Step 3: Design and manufacture the C33 ASIC product.
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6 Board Development (2) Board development process (example 2) Use the following procedure when the package and pin arrangement cannot be determined initially. Step 1: Create an evaluation board using the C33209 (general-purpose product), FPGA, and the required memory. Evaluate the performance and the FPGA circuit. Also, start software development at this time. Step 2: Create the target board (mass production version), and at the same time design and manufacture the C33 ASIC.
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7 Mounting Chapter 7 Mounting 7.1 Precautions on Mounting The following shows the precautions when designing the board and mounting the IC. Oscillation Circuit • Oscillation characteristics change depending on conditions (board pattern, components used, etc.). In particular, when a ceramic oscillator or crystal oscillator is used, use the oscillator manufacturer's recommended values for constants such as capacitance and resistance.
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7 Mounting Reset Circuit • The power-on reset signal which is input to the P_RESETX pin changes depending on conditions (power rise time, components used, board pattern, etc.). Decide the time constant of the capacitor and resistor after enough tests have been completed with the application product. • In order to prevent any occurrences of unnecessary resetting caused by noise during operating, components such as capacitors and resistors should be connected to the P_RESETX pin in the shortest line.
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7 Mounting Recommended Circuit A[23:0] VDD D[23:0] VDDE #RD AVDDE #EMEMRD #DRD DSIO #GARD #GAAS TST #WRL/#WR#WE #WRH/BSH EA3MD #DWR #HCAS EA10MD0 #LCAS #CExx/#RASx #CE10EX EA10MD1 #CE10IN #WAIT #X2SPD #BCLK #BUSREQ #BUSACK PLLC S1C33209/204/202 #BUSGET #NMI [The potential of the substrate PLLS0 External Bus #DMAREQx #DMAACKx #DMAENDx HSDMA OSC3 A/D input #ADTRG ADx OSC1 EXCLx TMx T8UFx OSC2 kxx I/O Pxx R1 C2 C1 X`tal2 or CR Rf2 PLLS1 SINx SOUTx #SCLKx #SRDYx Input *1 (back of the chip
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7 Mounting Arrangement of Signal Lines • In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit and analog input unit. • When a signal line is parallel with a high-speed line in long distance or intersects a high-speed line, noise may generated by mutual interference between the signals and it may cause a malfunction.
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7 Mounting 7.2 Others The positions (layout) of the following pins is extremely important to prevent incorrect operation of the end device when the C33 macros are used. In some cases, we may request consultation with the customer concerning these positions, depending on the pin arrangement table created by the customer.
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S1C33 ASIC DESIGN GUIDE ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.