User manual

TB-7Z-020-EMC Hardware User Manual
20
Rev.1.03
7.5. Memory
Zynq AP SoC contains a hardened PS memory interface unit. The memory interface unit includes a
dynamic memory controller and static memory interface modules.
7.5.1. DDR3
The board includes two DDR3 SDRAM memory components creating a 32-bit interface. The DDR3 is
connected to the hard memory controller in the PS.
The PS incorporates both the DDR controller and the associated PHY, including its own set of dedicated
I/Os. The PS DDR3 memory interface speeds up to 533MHz (1066Mbps) are supported.
Device: MT41J256M16RE-15E IT:D (Micron) 32 Meg x 16 x 8 banks (or compatible device)
Device Data Rate: 667MHz (1333Mbps)
The DDR3 interface is shown in Figure 7-8.
DDR3 SDRAM
4Gbit
MT41J256M16RE-
15E IT:D
(U1)
A[14:0] , BA[2:0]
XCAS , XRAS
XWE , XCS
ODT , XRESET
CK , XCK , CKE
DDR3 SDRAM
4Gbit
MT41J256M16RE-
15E IT:D
(U2)
DM[1:0]
DQ[15:0]
DQS[1:0] , XDQS[1:0]
DM[3:2]
DQ[31:16]
DQS[3:2] , XDQS[3:2]
ZYNQ
XC7Z020-1CLG484
PS Bank502
Figure 7-8 DDR3 Memory Connection