RM0403-3-E01 Application Manual Real Time Clock Module RX-8564LC Model Product Number RX-8564LC Q418564C0xxxx00
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RX − 8564 LC CONTENTS 1. Overview...................................................................................................................1 2. Block diagram.........................................................................................................1 3. Terminal description.............................................................................................2 3.1. Terminal connections ...............................................................................................
RX − 8564 LC Low power consumption / Small size thin model package I2C-Bus Interface Real Time Clock Module RX − 8564 LC • Built in frequency adjusted 32.768 kHz crystal unit. • Interface type : 400 kHz two-wire I2C-bus interface • Wide operating voltage range : 1.8 V to 5.5 V • Wide timekeeper voltage range : 1.0 V to 5.5 V ( at Ta = +25 °C ) • Low backup current : 275 nA ( Typ. ) / 3 V : C-MOS output with output control • 32.
RX − 8564 LC 3. Terminal description 3.1. Terminal connections RX − 8564 LC 1. N.C. 2. N.C. 3. N.C. 4. N.C. 12. 11. CLKOE # 12 #1 N.C. 10. VDD 9. CLKOUT #7 #6 5. /INT 8. SCL 7. SDA 6. GND VSOJ − 12pin 3.2. Pin Functions Signal I/O name SCL SDA Input Bi-Directional Function 2 This is the serial clock input pin for I C Bus communications. This pin's signal is used for input and output of address, data, and ACK bits, 2 synchronized with the serial clock used for I C communications.
RX − 8564 LC 4. External Dimensions / Marking Layout 4.1. External Dimensions RX − 8564 LC ( VSOJ − 12pin ) • External dimensions • Recommended soldering pattern 3.6 ± 0.2 2.5 #7 0.27 2.4 1.6 0.5 0.8 3.2 ( 0.4 ) 2.8 ± 0.2 2.4 0.8 # 12 #6 2.77 0.08 M 0.22 Min. 0 0.5 1.1 ± 0.1 #1 Unit : mm 0.08 4.2.
RX − 8564 LC 5. Absolute Maximum Ratings Parameter GND = 0 V Symbol Condition Rating Unit Supply Voltage VDD Between VDD and GND −0.5 to +6.5 V Supply Voltage IDD VDD pin −50 to 50 mA Input Voltage VI Input pin GND−0.5 to VDD+0.5 V Output Voltage VO /INT pin GND−0.5 to VDD+0.5 V DC Input Current II −10 to 10 mA DC Output Current IO −10 to 10 mA −55 to +125 °C Storage Temperature Range Stored bare product after unpacking TSTG 6.
RX − 8564 LC 8. Electrical Characteristics 8.1. DC characteristics Item * Unless otherwise specified, GND = 0 V , VDD = 1.8 V to 5.5 V , Ta = −40 °C to +85 °C Symbol Current consumption ∗ interface active Condition Min. Typ. Max. Unit fSCL = 400 kHz 800 µA fSCL = 100 kHz 200 µA IDD Current consumption fSCL = 0 Hz, VDD = 5.0 V 330 800 nA fSCL = 0 Hz, VDD = 3.0 V 275 700 nA ∗ CLKOUT = disabled ( CLKOE = GND ) fSCL = 0 Hz, VDD = 2.
RX − 8564 LC 8.2. AC electrical characteristics Item * Unless otherwise specified, GND = 0 V , VDD = 1.8 V to 5.5 V , Ta = −40 °C to +85 °C Symbol SCL clock frequency Condition Min. Typ. fSCL Max. Unit 400 kHz Start condition set-up time tSU; STA 0.6 µs Start condition hold time tHD; STA 0.6 µs Data set-up time tSU; DAT 100 ns Data hold time tHD; DAT 0 ns Stop condition set-up time tSU; STO 0.6 µs Bus free time between a STOP and START condition tBUF 1.
RX − 8564 LC 9. Reference data (1) Example of frequency and temperature characteristics × 10-6 θT = +25 °C Typ. α = -0.035 × 10-6 Typ. 1. Frequency and temperature characteristics can be approximated using the following equations. 0 Frequency ∆fT [ Finding the frequency stability ] ∆fT = α ( θT − θX ) 2 ! ∆fT ! α [ 1 / °C2 ] -50 ! θT [ °C ] ! θX [ °C ] -100 -150 -50 0 50 100 : Frequency deviation in any temperature : Coefficient of secondary temperature ( −0.035 ± 0.
RX − 8564 LC 10.
RX − 8564 LC 11. Application notes 1) Notes on handling This module uses a C-MOS IC to realize low power consumption. Carefully note the following cautions when handling. (1) Static electricity While this module has built-in circuitry designed to protect it against electrostatic discharge, the chip could still be damaged by a large discharge of static electricity. Containers used for packing and transport should be constructed of conductive materials.
RX − 8564 LC 12. Overview of Functions and Description of Registers 12.1. Overview of Functions 1) Clock functions This function is used to set and read out month, day, hour, date, minute, second, and year (last two digits) data. Any (two-digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2099. ∗ For details, see "13.1. Description of Registers".
RX − 8564 LC 12.2.
RX − 8564 LC 13. Description of Functions 13.1. Description of registers 13.1.1. Control register 1 ( Reg − 00 [h] ) Address [h] Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 Control 1 TEST 0 STOP 0 TEST 0 0 0 • This register is used to control stopping and starting of the clock function, calendar function, and other functions. 1) TEST bits (bit 7 and bit 3) These two TEST bits are for use by Seiko Epson Corporation. When initializing, be sure to write "0".
RX − 8564 LC 13.1.2. Control register 2 ( Reg − 01 [h] ) Address [h] Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 Control 2 0 × 0 TI / TP AF TF AIE TIE • This register is used to monitor various interrupt event settings and the conditions under which various interruptrelated events occur. 1) TI / TP bit ( Interrupt Signal Output Mode Select.
RX − 8564 LC 13.1.3. Clock counter ( Reg − 02 [h] to 04 [h] ) Address [h] Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 02 Seconds VL 40 20 10 8 4 2 1 03 Minutes × 40 20 10 8 4 2 1 04 Hours × × 20 10 8 4 2 1 • The clock counter counts seconds, minutes, and hours. • The data format is BCD format. For example, when the "seconds" register value is "0101 1001" it indicates 59 seconds.
RX − 8564 LC 13.1.4. Calendar counter ( Reg − 05 [h] , 07 [h] , 08 [h] ) Address [h] Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 05 Days × × 20 10 8 4 2 1 07 Months / Century C × × 10 8 4 2 1 08 Years 80 40 20 10 8 4 2 1 • The auto calendar function updates all dates, months, and years from January 1, 2001 to December 31, 2099. • The data format is BCD format. For example, a date register value of "0011 0001" indicates the 31st.
RX − 8564 LC 13.1.6. Alarm registers ( Reg − 09 [h] to 0C [h] ) Address [h] Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 09 Minute Alarm AE 40 20 10 8 4 2 1 0A Hour Alarm AE × 20 10 8 4 2 1 0B Day Alarm AE × 20 10 8 4 2 1 0C Weekday Alarm AE × × × × 4 2 1 • The AIE bit and AF bit can both be set or used when using alarm interrupt function to set interrupt events for dates, days, hours, minutes, etc.
RX − 8564 LC 13.1.9. CLKOUT output register (Reg - 0D [h]) Address [h] Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0D CLKOUT frequency FE × × × × × FD1 FD0 • This register is used to control clock output via the CLKOUT output pin. • This register is valid only when the CLKOE input pin is at high level, at which time clock output is enabled or disabled (stopped) depending on the settings in this register.
RX − 8564 LC 13.2. Fixed-cycle Timer Interrupt Function The fixed-cycle timer interrupt function generates an interrupt event periodically at any fixed cycle set between 244.14 µs and 255 minutes. There are two operation modes: "level interrupt mode" whereby the operation ends after one time, and "repeated interrupt mode" whereby the operation is automatically repeated.
RX − 8564 LC 3) Overview of fixed-cycle timer interrupt function (1) Changing the TE (Timer Enable) bit value from "0" to "1" starts operation of the fixed-cycle timer interrupt function. ∗ Before starting the fixed-cycle timer interrupt function each time, be sure to write a value (preset value/Reg-0F[h]) as the down counter value for the timer (when TE = "0"). (Note) Note with caution that the preset value must be set or reset to enable correct operation.
RX − 8564 LC 13.2.2. Related registers for function of timer interrupts. Address [h] Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 Control 2 0 × 0 TI / TP AF TF AIE TIE 0E Timer control TE × × × × × TD1 TD0 0F Timer 128 64 32 16 8 4 2 1 ∗ Before starting the fixed-cycle timer interrupt function each time, be sure to write a value (preset value/Reg-0F[h]) as the timer's down counter value (when TE = "0").
RX − 8564 LC 3) Down counter for fixed-cycle timer ( Timer Register ) This register is used to set the default (preset) value for the counter. Any count value from 1 (01 h) to 255 (FFh) can be set When the fixed-cycle timer interrupt function is operating, the down counter counts down one step per source clock cycle, and when the count value goes from 01h to 00h, an event such as changing the TF bit value to "1" occurs.
RX − 8564 LC 6) TIE bit ( Timer Interrupt Enable ) This bit is used to control output of interrupt signals from the /INT pin when a fixed-cycle timer interrupt event has occurred. When a "1" is written to this bit, occurrence of an interrupt event causes a low-level interrupt signal to be output from /INT pin. When a "0" is written to this bit, output from the /INT pin is prohibited (disabled).
RX − 8564 LC 13.2.4. Diagram of fixed-cycle timer interrupt function 13.2.4.1. Operation example of level interrupt mode ( TI / TP = " 0 " ) • After an interrupt event has occurred, this function operates only once. Start of fixed-cycle timer operation (6) (1) TE bit ∗ Even if the TE bit is cleared to zero, the TF bit value is held as "1". Also, the /INT pin is not canceled. The TF bit value is held until it is directly cleared to zero.
RX − 8564 LC 13.2.4.2. Operation example of repeated interrupt mode ( TI / TP = " 1 " ) • After an interrupt event has occurred, execution of the operation is automatically repeated continuously.
RX − 8564 LC 13.3. Alarm Interrupt Function The alarm interrupt generation function generates interrupt events for alarm settings such as date, day, hour, and minute settings. When an interrupt event occurs, the AF bit value is set to "1" and the /INT pin goes to low level to indicate that an event has occurred. ∗ When an alarm interrupt event occurs, low-level output from /AIRQ is not automatically reset (it can be reset only intentionally) and the low-level status of /AIRQ is retained.
RX − 8564 LC 13.3.2.
RX − 8564 LC 3) AIE bit ( Alarm Interrupt Enable ) This bit is used to control interrupt signal output from the /INT pin when an alarm interrupt event has occurred. Writing "1" to this bit causes a low-level interrupt signal to be output from the /INT pin when an interrupt event occurs. When a "0" is written to this bit, output from the /INT pin is prohibited (disabled).
RX − 8564 LC 13.4. /INT "L" Interrupt Output When Interrupt Function Operates 1) Setting interrupt events to occur in response to /INT "L" interrupt output The /INT interrupt output pin is shared as the output pin for two kinds of interrupt events: events related to the fixed-cycle timer interrupt function and events related to the alarm interrupt function.
RX − 8564 LC 13.5. Flow Charts • The flow charts shown below are intended as examples only. ∗ These examples are written to be easily understood, and therefore they may not be as efficient as the actual processing. ∗ Ways to boost processing efficiency include setting several processes as parallel processes and changing the sequence of operations in areas where it does not create any problems. (Some of the processing described here may not be necessary under certain use conditions.
RX − 8564 LC 3) Example of processing to recover from backup mode Backup recovery processing ∗1 No ( VL = " 1 " ) ∗2 ∗1) Check the VL bit (Voltage Low Flag). VL = " 0 " ? Yes ( VL = " 0 " ) ∗3 Initialization ∗2) When the VL bit = "1", it may be due to an error during backup (clock data or register settings may have been lost, due to a voltage drop, etc.), so be sure to initialize. ∗3) Be sure to initialize all registers. (For further description of initialization, see "Initialization" below.
RX − 8564 LC 6) Example of timer interrupt function setting i. Cancel timer interrupt function Set timer interrupt function • Zero-clear the TE bit to stop the timer interrupt function. TE ← " 0 " • Zero-clear the TF bit and TIE bit to cancel the previous timer interrupt output (/IRQ output). TF ← " 0 " TIE ← " 0 " ∗1 ∗1 • Select the operation mode (one-shot interrupt or repeated continuous interrupts).
RX − 8564 LC 13.6. Reading/Writing Data via the I2C Bus Interface 13.6.1. Overview of I2C-BUS 2 The I C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination of these two signals is used to transmit and receive communication start/stop signals, data transfer signals, acknowledge signals, and so on. Both the SCL and SDA signals are held at high level whenever communications are not being performed.
RX − 8564 LC 13.6.3. Starting and stopping I2C bus communications START Repeated START(RESTART) condition condition STOP condition SCL [S] [ Sr ] [P] SDA 1 s ( Max. ) 1) START condition, repeated START condition, and STOP condition (1) START condition • The SDA level changes from high to low while SCL is at high level. (2) STOP condition • This condition regulates how communications on the I2C-BUS are terminated. The SDA level changes from low to high while SCL is at high level.
RX − 8564 LC 13.6.4. Data transfers and acknowledge responses during I2C-BUS communications 1) Data transfers Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount (bytes) of data that are transferred between the START condition and STOP condition. (However, the transfer time must be no longer than 1 seconds.) The address auto increment function operates during both write and read operations.
RX − 8564 LC 13.6.6. I2C bus protocol In the following sequence descriptions, it is assumed that the CPU is the master and the [ 8564 ] is the slave. 1) Address specification write sequence Since the [ 8564 ] includes an address auto increment function, once the initial address has been specified, the [ 8564 ] increments (by one byte) the receive address each time data is transferred. (1) CPU transfers start condition [S]. (2) CPU transmits the [ 8564 ] 's slave address with the R/W bit set to write mode.
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