Datasheet
70
Real time clock module
CS1
VIH
(
CS1
)
VIH
VIH
VIH
VIH
VIH
VIH VIH
VIL
VIL
VIL
VIH
VIL
VIL
VIL
VIH
(
CS1
)
tSU
(
CS1
)
tSU
(
A-ALE
)
tH
(
ALE-A
)
tSU
(
ALE-W
)
tSU
(
D-W
)
tSU
(
W-ALE
)
tSU
(
R-ALE
)
t
W
(
ALE
)
CS0
ALE
WR
A0 to A3
D0 to D3
tH
(
CS1
)
tH
(
W-D
)
tW
(
W
)
CS1
CS1
CS0 or WR not occurred
CS
1
VIH
(
CS1
)
1/5VDD
VDD
4V 4V
V
IH2 VIH2
VIL2 VIL2
tCDR tR
VIH
VIH
V
OH
V
OL
V
OH
V
OL
VIH
VIH VIH
VIL
VIL
VIH
VIL
VIL
VIL
VIL
VIH
(
CS1
)
tSU
(
CS1
)
tSU
(
A-ALE
)
tH
(
ALE-A
)
tSU
(
ALE-R
)
tPZV
(
R-Q
)
tPVZ
(
R-Q
)
tSU
(
R-ALE
)
trnc
(
R
)
t
W
(
ALE
)
CS0
ALE
RD
A0 to A3
D0 to D3
tH
(
CS1
)
2 to 4V
≤
Data storage mode
Interface possible
with external
terminals
Interface possible
with the external
terminals
OSC
DIVIDER
READ • WRITE
CONTROL
ADDRESS LATCH
DATA BUS • BUFFER
ADDRESS DECODER
RD WR CS1 ALE CS0 A0 D0 D1 D2 D3A1 A2 A3
STD•P
64 HZ
REST
STOP
30ADJ
BUSY
HOLD
CARRY PER
SEC.
CARRY PER
MIN.
CARRY PER
HOUR
4
4
4
4
4
IRQFLAG
24/12
Seconds Minutes Hours
Days
Months Years
Week
Sec 1 Sec 10 Min 1 Min 10 Hou 1 Hou 10 Day 1 Day 10 Mon 1 Mon 10 Yea 1 Yea 10 Reg D Reg E Reg F
Register table
Switching characteristics
(
with ALE
)
Read mode
(
with ALE
)
Write mode
(
with ALE
)
Data holding timing
Block diagram
(
V
DD
=
5V
±
0.5V
)
0=“L” level,1=“H” level, REST = RESET ITRPT/ STND=INTERRUPT/STANDARD
1
)
Bit
does not exist.
2
)
Please mask AM/PM bit with 10's of hours operations.
3
)
Busy is read only. IRQ can only. IRQ can only be set low (“O”).
4
)
5
)
TEST bit should be “O”.
(
Please connect ALE to V
DD if the microprocessor does not have an ALE output.
)
∗
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
S1
S10
MI 1
MI10
H1
H10
D1
D10
MO
1
MO
10
Y1
Y10
W
Reg
D
Reg
E
Reg
F
D3
s8
∗
mi
8
∗
h
8
∗
d
8
∗
mo
8
∗
y
8
y80
∗
30 sec.
ADJ
t1
TEST
D2
s4
s40
mi4
mi40
h4
PM/AM
d4
∗
mo
4
∗
y
4
y40
w4
IRQ
FLAG
t0
24/12
D
1
s2
s20
mi2
mi20
h2
h20
d2
d20
mo2
∗
y
2
y20
w2
BUSY
ITRPT
/STND
STOP
D0
s1
s10
mi1
mi10
h1
h10
d1
d10
mo1
mo10
y1
y10
w1
HOLD
MASK
REST
Count
Value
0 to 9
0 to 5
0 to 9
0 to 5
0 to 9
0 to 2
or
0 to 1
0 to 9
0 to 3
0 to 9
0 to 1
0 to 9
0 to 6
-----
Remarks
1- second digit register
10- second digit register
1- minute digit register
10- minute digit register
1- hour digit register
PM/AM,10- hours digit register
1- day digit register
10 -day digit register
1- month digit register
10- month digit register
1- year digit register
10- year digit register
Week register
Control Register D
Control Register E
Control Register F
Item
CS
1 setup time
Address setup time before ALE
Address hold time after ALE
ALE pulse width
ALE setup time before WRITE
ALE setup time before READ
ALE setup time after WRITE
ALE setup time after READ
WRITE pulse width
DATA delay time after READ
DATA Hold time after READ
DATA setup time before WRITE
DATA hold time after WRITE
CS
1 hold time
READ/WRITE recovery time
Symbol
t
SU (CS1)
t
SU (A-ALE)
t
H (ALE-A)
t
W (ALE)
t
SU (ALE-W)
t
SU (ALE-R)
t
SU (W-ALE)
t
SU (R-ALE)
t
W (W)
t
PZV (R-Q)
t
PVZ (R-Q)
t
SU (D-W)
t
H (W-D)
t
H (CS1)
t
REC (R/W)
Condition
C
L=150pF
Min.
1000
50
50
80
0
0
50
50
120
----
0
80
10
1000
200
Max.
----
120
70
----
Unit
ns
Address
Register
Data Bit
1
0
PM/AM
PM
AM
ITRPT/STND
ITRPT
STND
24/12
24
12
Data