Specifications

Selbsttest ZVx
1043.0009.50 4.6 E-3
4.3.3 Processor Structure
In addition to a 586 CPU, the network analyzer also comprises three 32-bit transputers T805 and one
16-bit transputer T225. Two DSPs are provided for digital signal processing.
The 586 CPU handles the complete data exchange with the peripheral devices, such as e.g. keyboard
entry, display of the softkeys and operation via IEC bus. Irrespective of this, the transputers control the
measurement run, consider correction factors and represent the trace on the display. For this purpose,
the transputers receive the current instrument settings from the 586 CPU via a link adapter, which
constitutes the connection between the ISA bus of the CPU board and a transputer link of the T805 on
the graphics board (in the following referred to as GTP = graphics transputer). The T225 on the graphics
and the two T805 on the Measurement Control Unit (MCU) are coupled to the GTP via further transputer
links. The T225 exclusively serves as interface between the GTP and the chip set for the graphics.
4.3.3.1 Measurement Control Unit
The Measurement Control Unit (MCU) performs the following tasks:
Control of the analog modules:
• Via the IBUS (serial bus), the settings of the ZVR that are not critical with respect to time are made by
the setting transputer and the self test signals on the modules are selected.
• The FRNBUS is a parallel setting bus for the synthesizer module.
• The GSC(Global S
equence Control) performs the time-critical settings in the network analyzer.
Processing of the measured values:
• The stream of measured data coming from the converters is preprocessed by two DSPs (digital
filtering and digital mixer).
• The measurement transputer is intended for further processing, in particular for system error
correction.
Recording of selftest signals:
• The selftest signals selected via multiplexer are converted by an A/D converter.