Specifications

STATus Subsystem ZVx
1043.0009.50 3.124 E-15
STATus:OPERation:CONDition?
This command queries the CONDition section of the STATus:OPERation register.
Syntax: STATus:OPERation:CONDition?
Example: "STAT:OPER:COND?"
Features: *RST value: –
SCPI: conforming
Readout does not delete the contents of the CONDition section. The value returned reflects the
current hardware status.
STATus:OPERation:ENABle
This command sets the bits of the ENABle section of the STATus:QUEStionable register.
Syntax: STATus:OPERation:ENABle 0 to 65535
Example: "STAT:OPER:ENAB 65535"
Features: *RST value: –
SCPI: conforming
The ENABle register selectively enables the individual events of the associated EVENt section for
the sum bit in the status byte.
STATus:OPERation:PTRansition
This command sets the edge detectors of all bits of the STATus:OPERation register from 0 to 1 for
the transitions of the CONDition bit.
Syntax: STATus:OPERation:PTRansition 0 to 65535
Example: "STAT:OPER:PTR 65535"
Features: *RST value: –
SCPI: conforming
STATus:OPERation:NTRansition
This command sets the edge detectors of all bits of the STATus:OPERation register from 1 to 0 for
the transitions of the CONDition bit.
Syntax: STATus:OPERation:NTRansition 0 to 65535
Example: "STAT:OPER:NTR 65535"
Features: *RST value: –
SCPI: conforming
STATus:PRESet
This command resets the edge detectors and ENABle parts of all registers to a defined value. All
PTRansition parts are set to FFFFh, i.e., all transitions from 0 to 1 are detected. All NTRansition
parts are set to 0, i.e., a transition from 1 to 0 in a CONDition bit is not detected. The ENABle part of
the STATus:OPERation and STATus:QUEStionable registers are set to 0, i.e., all events in these
registers are not passed on.
Syntax: STATus:PRESet
Example: "STAT:PRES"
Features: *RST value: –
SCPI: conforming