MF1574-01 CMOS 32-BIT SINGLE CHIP MICROCOMPUTER S1C33L03 Technical Manual S1C33L03 PRODUCT PART S1C33L03 FUNCTION PART
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S1C33L03 Technical Manual This manual describes the hardware specifications of the Seiko Epson original 32-bit microcomputer S1C33L03. S1C33L03 PRODUCT PART Describes the hardware specifications of the S1C33L03 except for details of the peripheral circuits. S1C33L03 FUNCTION PART Describes details of all the peripheral circuit blocks for the S1C33 Family microcomputers. Refer to the "S1C33000 Core CPU Manual" for details of the S1C33000 32-bit RISC CPU.
TABLE OF CONTENTS S1C33L03 PRODUCT PART Table of Contents 1 Outline..................................................................................................................................... A-1 1.1 Features.....................................................................................................................................A-1 1.2 Block Diagram ...........................................................................................................................A-3 1.
TABLE OF CONTENTS Appendix A External Device Interface Timings.......................................... A-113 A.1 A.2 A.3 A.4 A.5 A.6 DRAM (70ns)........................................................................................................................ A-114 DRAM (60ns)........................................................................................................................ A-117 ROM and Burst ROM .....................................................................
TABLE OF CONTENTS S1C33L03 FUNCTION PART Table of Contents I OUTLINE I-1 INTRODUCTION ............................................................................................................ B-I-1-1 I-2 BLOCK DIAGRAM......................................................................................................... B-I-2-1 I-3 LIST OF PINS................................................................................................................. B-I-3-1 List of External I/O Pins.......
TABLE OF CONTENTS Bus Clock.................................................................................................................................. B-II-4-17 Bus Speed Mode .......................................................................................................... B-II-4-18 Bus Clock Output .......................................................................................................... B-II-4-18 Bus Cycles in External System Interface......................................
TABLE OF CONTENTS III PERIPHERAL BLOCK III-1 INTRODUCTION ......................................................................................................... B-III-1-1 III-2 PRESCALER............................................................................................................... B-III-2-1 Configuration of Prescaler......................................................................................................... B-III-2-1 Source Clock .............................................
TABLE OF CONTENTS III-7 CLOCK TIMER ............................................................................................................B-III-7-1 Configuration of Clock Timer..................................................................................................... B-III-7-1 Control and Operation of the Clock Timer ................................................................................ B-III-7-2 Interrupt Function...................................................................
TABLE OF CONTENTS IV ANALOG BLOCK IV-1 INTRODUCTION .........................................................................................................B-IV-1-1 IV-2 A/D CONVERTER .......................................................................................................B-IV-2-1 Features and Structure of A/D Converter .................................................................................B-IV-2-1 I/O Pins of A/D Converter...........................................................
TABLE OF CONTENTS VI SDRAM CONTROLLER BLOCK VI-1 INTRODUCTION......................................................................................................... B-VI-1-1 VI-2 SDRAM INTERFACE ................................................................................................. B-VI-2-1 Outline of SDRAM Interface......................................................................................................B-VI-2-1 SDRAM Controller Block Diagram .......................................
TABLE OF CONTENTS Virtual Screen and View Port .................................................................................... B-VII-2-23 Inverting and Blanking the Display............................................................................ B-VII-2-25 Portrait Mode ............................................................................................................. B-VII-2-25 Power Save.....................................................................................................
S1C33L03 PRODUCT PART
1 OUTLINE A-1 1 Outline The S1C33L03 is a Seiko Epson original 32-bit microcomputer with a built-in LCD controller. It features high speed, low power and low-voltage operation and is most suitable for portable equipment that needs display function, such as information terminals, E-mail terminals, electronic dictionaries.
1 OUTLINE Interrupt controller: Possible to invoke DMA Input interrupt 10 types (programmable) DMA controller interrupt 5 types 16-bit programmable timer interrupt 12 types 8-bit programmable timer interrupt 4 types Serial interface interrupt 6 types A/D converter interrupt 1 type Clock timer interrupt 1 type Shared with the I/O pins for internal peripheral circuits Input port 13 bits I/O port 29 bits General-purpose input and output ports: External bus interface BCU (bus control unit) built-in • 24-bit
1 OUTLINE A-1 1.
1 OUTLINE 1.3 Pin Description 1.3.1 Pin Layout Diagram (plastic package) QFP20-144pin 108 73 109 72 INDEX 144 37 1 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 36 Pin name No.
1 OUTLINE A-1 1.3.2 Pin Functions Table 1.3.1 List of Pins for Power Supply System Pin name VDD VSS VDDE AVDDE Pin No. I/O Pull-up 8,51,78,127 3,27,45,66, 82,98,105, 114,116,136 21,59,91,132 36 – – – – Power supply (+) for the internal logic Power supply (-); GND Function – – – – Power supply (+) for the I/O block Analog system power supply (+); AVDDE = VDDE Pin No.
1 OUTLINE Pin No.
1 OUTLINE A-1 Table 1.3.3 List of Pins for HSDMA Control Signals Pin name K50 #DMAREQ0 K51 #DMAREQ1 K53 #DMAREQ2 K54 #DMAREQ3 P32 #DMAACK0 #SRDY3 HDQM Pin No.
1 OUTLINE Table 1.3.4 List of Pins for Internal Peripheral Circuits Pin name K50 #DMAREQ0 K51 #DMAREQ1 K52 #ADTRG K53 #DMAREQ2 K54 #DMAREQ3 K60 AD0 K61 AD1 K62 AD2 K63 AD3 K64 AD4 K65 AD5 K66 AD6 K67 AD7 P00 SIN0 P01 SOUT0 P02 #SCLK0 P03 #SRDY0 P04 SIN1 #DMAACK2 Pin No.
1 OUTLINE Pin name Pin No.
1 OUTLINE Pin No. I/O Pull-up P26 TM4 SOUT2 Pin name 6 I/O – P27 TM5 SIN2 7 I/O – P30 #WAIT #CE4&5 75 I/O – P31 #BUSGET #GARD GPIO2 74 I/O – P32 #DMAACK0 #SRDY3 HDQM 73 I/O – P33 #DMAACK1 SIN3 SDA10 72 I/O – P34 #BUSREQ #CE6 GPIO0 71 I/O – P35 #BUSACK GPIO1 70 I/O – A-10 Function P26: TM4: SOUT2: I/O port when CFP26(D6/0x402D8) = "0" (default) 16-bit timer 4 output when CFP26(D6/0x402D8) = "1" Serial I/F Ch.
1 OUTLINE A-1 Table 1.3.5 List of Pins for LCD Controller Pin No. I/O Pull-up FPDAT[7:4] Pin name 13–16 O – FPDAT[3:0] GPO[6:3] FPFRAME FPLINE FPSHIFT DRDY(MOD) (FPSHIFT2) LCDPWR 17–20 O – 23 24 25 22 O O O O – – – – 26 O – Pin name Pin No. I/O Pull-up 68 67 129 128 112,113 I O I O I – – – – – 115 – – Pin No.
2 POWER SUPPLY 2 Power Supply This chapter explains the operating voltage of the S1C33L03. 2.1 Power Supply Pins The S1C33L03 has the power supply pins shown in Table 2.1.1. Pin name VDD VSS VDDE AVDDE Table 2.1.1 Power Supply Pins Pin No. Function 8,51,78,127 Power supply (+) for the internal logic 3,27,45,66,82,98,105,114,116,136 Power supply (-); GND 21,59,91,132 Power supply (+) for the I/O block 36 Analog system power supply (+); AVDDE = VDDE 1.8 to 3.6 V VDD CPU core 1.8 to 5.
2 POWER SUPPLY A-1 2.3 Power Supply for I/O Interface (VDDE) A-2 The VDDE voltage is used for interfacing with external I/O signals. For the output interface of the S1C33L03, the VDDE voltage is used as high level and the VSS voltage as low level. Normally, supply the same voltage level as VDD. It can be supplied separately from VDD for 5 V interface. The VSS pin is used for the ground common with VDD. The following voltage is enabled for VDDE: VDDE = 1.8 V to 5.
3 INTERNAL MEMORY 3 Internal Memory This chapter explains the internal memory configuration. Figure 3.1 shows the S1C33L03 memory map.
3 INTERNAL MEMORY A-1 3.2 RAM The S1C33L03 has a built-in 8KB RAM. The RAM is allocated to Area 0, address 0x0000000 to address 0x0001FFF. The internal RAM is a 32-bit sized device and data can be read/written in 1 cycle regardless of data size (byte, halfword or word).
4 PERIPHERAL CIRCUITS 4 Peripheral Circuits This chapter lists the built-in peripheral circuits and the I/O memory map. For details of the circuits, refer to the "S1C33L03 FUNCTION PART". 4.1 List of Peripheral Circuits The S1C33L03 consists of the C33 Core Block, C33 SDRAM Controller Block, C33 Peripheral Block, C33 DMA Block, C33 Analog Block, and C33 LCD Controller Block.
4 PERIPHERAL CIRCUITS A-1 4.2 I/O Memory Map Table 4.2.
4 PERIPHERAL CIRCUITS Register name Address Bit Name Function 16-bit timer 3 clock control register 004014A D7–4 – (B) D3 P16TON3 D2 P16TS32 D1 P16TS31 D0 P16TS30 reserved 16-bit timer 3 clock control 16-bit timer 3 clock division ratio selection 16-bit timer 4 clock control register 004014B D7–4 – (B) D3 P16TON4 D2 P16TS42 D1 P16TS41 D0 P16TS40 reserved 16-bit timer 4 clock control 16-bit timer 4 clock division ratio selection 16-bit timer 5 clock control register 004014C D7–4 – (B) D3 P16TON5
4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name 8-bit timer 2/3 clock control register D7 D6 D5 D4 P8TON3 P8TS32 P8TS31 P8TS30 004014E (B) D3 D2 D1 D0 P8TON2 P8TS22 P8TS21 P8TS20 A/D clock 004014F control register (B) D7–4 D3 D2 D1 D0 Clock timer Run/Stop register D7–2 – D1 TCRST D0 TCRUN 0040151 (B) Clock timer 0040152 interrupt (B) control register Clock timer 0040153 divider register (B) Clock timer second register 0040154 (B) – PSONAD PSAD2 PSAD1 PSAD0 Function 8-bit timer
4 PERIPHERAL CIRCUITS Register name Address Bit Clock timer 0040155 minute register (B) D7–6 D5 D4 D3 D2 D1 D0 – TCHD5 TCHD4 TCHD3 TCHD2 TCHD1 TCHD0 reserved Clock timer minute counter data TCHD5 = MSB TCHD0 = LSB Clock timer hour register D7–5 D4 D3 D2 D1 D0 – TCDD4 TCDD3 TCDD2 TCDD1 TCDD0 Clock timer 0040157 day (low-order) (B) register D7 D6 D5 D4 D3 D2 D1 D0 Clock timer day (highorder) register 0040158 (B) Clock timer minute comparison register 0040159 (B) Clock timer hour comparison reg
4 PERIPHERAL CIRCUITS A-1 Register name Address Bit 8-bit timer 0 0040160 control register (B) D7–3 D2 D1 D0 Name Function – PTOUT0 PSET0 PTRUN0 reserved 8-bit timer 0 clock output control 8-bit timer 0 preset 8-bit timer 0 Run/Stop control Setting – 1 On 1 Preset 1 Run 0 Off 0 Invalid 0 Stop Init. R/W Remarks – 0 – 0 – 0 when being read. R/W W 0 when being read.
4 PERIPHERAL CIRCUITS Register name Address Bit Name Function 8-bit timer 3 004016C D7–3 – control register (B) D2 PTOUT3 D1 PSET3 D0 PTRUN3 reserved 8-bit timer 3 clock output control 8-bit timer 3 preset 8-bit timer 3 Run/Stop control 8-bit timer 3 reload data register 004016D (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD37 RLD36 RLD35 RLD34 RLD33 RLD32 RLD31 RLD30 8-bit timer 3 reload data RLD37 = MSB RLD30 = LSB 8-bit timer 3 counter data register 004016E (B) D7 D6 D5 D4 D3 D2 D1 D0 PTD37 PTD36 PTD35 P
4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name Function Setting Init. R/W Remarks Watchdog 0040170 timer write(B) protect register D7 WRWD D6–0 – EWD write protection – 1 Write enabled 0 Write-protect – 0 – R/W – 0 when being read. Watchdog timer enable register D7–2 – D1 EWD D0 – – Watchdog timer enable – – 1 NMI enabled 0 NMI disabled – – 0 – – 0 when being read. R/W – 0 when being read.
4 PERIPHERAL CIRCUITS Register name Address Bit Name Power control register D7 D6 CLKDT1 CLKDT0 System clock division ratio selection D5 D4–3 D2 D1 D0 PSCON – CLKCHG SOSC3 SOSC1 Prescaler On/Off control reserved 1 OSC3 CPU operating clock switch High-speed (OSC3) oscillation On/Off 1 On Low-speed (OSC1) oscillation On/Off 1 On 0040180 (B) Function Setting CLKDT[1:0] 1 1 1 0 0 1 0 0 1 On R/W 1 0 1 1 1 R/W – Writing 1 not allowed. R/W R/W R/W – 0 0 – R/W – 0 1 0 0 – 0 when being read.
4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name Function Serial I/F Ch.0 transmit data register 00401E0 (B) D7 D6 D5 D4 D3 D2 D1 D0 TXD07 TXD06 TXD05 TXD04 TXD03 TXD02 TXD01 TXD00 Serial I/F Ch.0 transmit data TXD07(06) = MSB TXD00 = LSB 0x0 to 0xFF(0x7F) Serial I/F Ch.0 receive data register 00401E1 (B) D7 D6 D5 D4 D3 D2 D1 D0 RXD07 RXD06 RXD05 RXD04 RXD03 RXD02 RXD01 RXD00 Serial I/F Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit Serial I/F Ch.1 transmit data register 00401E5 (B) D7 D6 D5 D4 D3 D2 D1 D0 TXD17 TXD16 TXD15 TXD14 TXD13 TXD12 TXD11 TXD10 Name Serial I/F Ch.1 transmit data TXD17(16) = MSB TXD10 = LSB Function 0x0 to 0xFF(0x7F) X X X X X X X X Serial I/F Ch.1 receive data register 00401E6 (B) D7 D6 D5 D4 D3 D2 D1 D0 RXD17 RXD16 RXD15 RXD14 RXD13 RXD12 RXD11 RXD10 Serial I/F Ch.
4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name Function Serial I/F Ch.2 00401F3 control register (B) D7 D6 D5 D4 D3 D2 D1 D0 TXEN2 RXEN2 EPR2 PMD2 STPB2 SSCK2 SMD21 SMD20 Ch.2 transmit enable Ch.2 receive enable Ch.2 parity enable Ch.2 parity mode selection Ch.2 stop bit selection Ch.2 input clock selection Ch.2 transfer mode selection – DIVMD2 IRTL2 IRRL2 IRMD21 IRMD20 reserved Ch.2 async. clock division ratio Ch.2 IrDA I/F output logic inversion Ch.2 IrDA I/F input logic inversion Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit A/D conversion 0040240 result (low(B) order) register D7 D6 D5 D4 D3 D2 D1 D0 Name ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 Function 0 0 0 0 0 0 0 0 R – 0x0 to 0x3FF (high-order 2 bits) – 0 0 – R – – 0 0 0 D7–2 – D1 ADD9 D0 ADD8 – A/D converted data (high-order 2 bits) ADD9 = MSB A/D trigger register D7–6 D5 D4 D3 – MS TS1 TS0 – A/D conversion mode selection A/D conversion trigger selection D2 D1 D0 CH2 CH1 CH0 A/D conversion channel stat
4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Port input 0/1 0040260 interrupt (B) priority register D7 D6 D5 D4 D3 D2 D1 D0 – PP1L2 PP1L1 PP1L0 – PP0L2 PP0L1 PP0L0 reserved Port input 1 interrupt level – 0 to 7 reserved Port input 0 interrupt level – 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 – PP3L2 PP3L1 PP3L0 – PP2L2 PP2L1 PP2L0 reserved Port input 3 interrupt level – 0 to 7 reserved Port input 2 interrupt level – 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 – PK1L2 PK1L1 PK1L0 – PK0L2 PK0L1 PK0L0 reserve
4 PERIPHERAL CIRCUITS Register name Address Bit 8-bit timer, 0040269 serial I/F Ch.0 (B) interrupt priority register D7 D6 D5 D4 D3 D2 D1 D0 – PSIO02 PSIO01 PSIO00 – P8TM2 P8TM1 P8TM0 reserved Serial interface Ch.0 interrupt level – 0 to 7 reserved 8-bit timer 0–3 interrupt level – 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 – PAD2 PAD1 PAD0 – PSIO12 PSIO11 PSIO10 reserved A/D converter interrupt level – 0 to 7 reserved Serial interface Ch.
4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name Function Key input, 0040270 port input 0–3 (B) interrupt enable register D7–6 D5 D4 D3 D2 D1 D0 – EK1 EK0 EP3 EP2 EP1 EP0 reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 DMA interrupt 0040271 enable register (B) D7–5 D4 D3 D2 D1 D0 – EIDMA EHDM3 EHDM2 EHDM1 EHDM0 reserved IDMA High-speed DMA Ch.3 High-speed DMA Ch.2 High-speed DMA Ch.1 High-speed DMA Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit Key input, 0040280 port input 0–3 (B) interrupt factor flag register D7–6 D5 D4 D3 D2 D1 D0 – FK1 FK0 FP3 FP2 FP1 FP0 Name reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 Function DMA interrupt factor flag register 0040281 (B) D7–5 D4 D3 D2 D1 D0 – FIDMA FHDM3 FHDM2 FHDM1 FHDM0 reserved IDMA High-speed DMA Ch.3 High-speed DMA Ch.2 High-speed DMA Ch.1 High-speed DMA Ch.
4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name Port input 0–3, high-speed DMA Ch. 0/1, 16-bit timer 0 IDMA request register D7 D6 D5 D4 D3 D2 D1 D0 R16TC0 R16TU0 RHDM1 RHDM0 RP3 RP2 RP1 RP0 16-bit timer 0 comparison A 16-bit timer 0 comparison B High-speed DMA Ch.1 High-speed DMA Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit Name High-speed DMA Ch.0/1 trigger set-up register D7 D6 D5 D4 HSD1S3 HSD1S2 HSD1S1 HSD1S0 High-speed DMA Ch.1 trigger set-up D3 D2 D1 D0 HSD0S3 HSD0S2 HSD0S1 HSD0S0 High-speed DMA Ch.0 trigger set-up D7 D6 D5 D4 HSD3S3 HSD3S2 HSD3S1 HSD3S0 High-speed DMA Ch.3 trigger set-up D3 D2 D1 D0 HSD2S3 HSD2S2 HSD2S1 HSD2S0 High-speed DMA Ch.2 trigger set-up High-speed DMA Ch.
4 PERIPHERAL CIRCUITS A-1 Register name Address K5 function select register Bit Name Function 00402C0 D7–5 – (B) D4 CFK54 D3 CFK53 D2 CFK52 D1 CFK51 D0 CFK50 reserved K54 function selection K53 function selection K52 function selection K51 function selection K50 function selection K5 input port data register 00402C1 D7–5 – (B) D4 K54D D3 K53D D2 K52D D1 K51D D0 K50D reserved K54 input port data K53 input port data K52 input port data K51 input port data K50 input port data K6 function select regis
4 PERIPHERAL CIRCUITS Register name Address Bit Interrupt factor 00402C5 FP function switching register D7 D6 T8CH5S0 SIO3TS0 8-bit timer 5 underflow SIO Ch.3 transmit buffer empty D5 D4 T8CH4S0 SIO3RS0 8-bit timer 4 underflow SIO Ch.3 receive buffer full D3 SIO2TS0 SIO Ch.2 transmit buffer empty D2 SIO3ES0 SIO Ch.3 receive error D1 SIO2RS0 SIO Ch.2 receive buffer full D0 SIO2ES0 SIO Ch.
4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name Function Key input interrupt (FPK0) input comparison register 00402CC D7–5 – (B) D4 SCPK04 D3 SCPK03 D2 SCPK02 D1 SCPK01 D0 SCPK00 reserved FPK04 input comparison FPK03 input comparison FPK02 input comparison FPK01 input comparison FPK00 input comparison Key input interrupt (FPK1) input comparison register 00402CD D7–4 – (B) D3 SCPK13 D2 SCPK12 D1 SCPK11 D0 SCPK10 reserved FPK13 input comparison FPK12 input comparison FPK11 input comparison
4 PERIPHERAL CIRCUITS Register name Address Bit P1 I/O control register 00402D6 (B) D7 D6 D5 D4 D3 D2 D1 D0 Port SIO function extension register 00402D7 D7–4 – D3 SSRDY3 reserved Serial I/F Ch.3 SRDY selection 1 #SRDY3 D2 SSCLK3 Serial I/F Ch.3 SCLK selection 1 #SCLK3 D1 SSOUT3 Serial I/F Ch.3 SOUT selection 1 SOUT3 D0 SSIN3 Serial I/F Ch.
4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Port function extension register D7 D6 D5 D4 D3 D2 D1 CFEX7 CFEX6 CFEX5 CFEX4 CFEX3 CFEX2 CFEX1 P07 port extended function P06 port extended function P05 port extended function P04 port extended function P31 port extended function P21 port extended function P10, P11, P13 port extended function D0 CFEX0 P12, P14 port extended function DF DE DD DC – A18SZ A18DF1 A18DF0 DB DA D9 D8 – A18WT2 A18WT1 A18WT0 D7 D6 D5 D4 – A16SZ A16DF1 A16DF0 D3 D2
4 PERIPHERAL CIRCUITS Register name Address Bit Areas 12–11 0048124 set-up register (HW) DF–7 D6 D5 D4 – A12SZ A12DF1 A12DF0 D3 D2 D1 D0 – A12WT2 A12WT1 A12WT0 DF DE DD DC Areas 10–9 0048126 set-up register (HW) Areas 8–7 0048128 set-up register (HW) A-40 Name Function Setting Init. R/W Remarks reserved – Areas 12–11 device size selection 1 8 bits 0 16 bits Areas 12–11 A18DF[1:0] Number of cycles 1 1 3.5 output disable delay time 1 0 2.5 0 1 1.5 0 0 0.
4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name Areas 6–4 004812A DF–E – set-up register (HW) DD A6DF1 DC A6DF0 Function reserved Area 6 output disable delay time Setting – Number of cycles 3.5 2.5 1.5 0.5 – A6WT[2:0] Wait cycles 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 – 1 8 bits 0 16 bits A5DF[1:0] Number of cycles 1 1 3.5 1 0 2.5 0 1 1.5 0 0 0.5 A6DF[1:0] 1 1 1 0 0 1 0 0 Init. R/W Remarks – 1 1 – 0 when being read. R/W – 1 1 1 – 0 when being read.
4 PERIPHERAL CIRCUITS Register name Address Bit Name Function DRAM timing 0048130 DF–C – reserved set-up register (HW) DB A3EEN Area 3 emulation DA CEFUNC1 #CE pin function selection D9 CEFUNC0 Setting Init. R/W Remarks – 1 Internal ROM 0 Emulation CEFUNC[1:0] #CE output 1 x #CE7/8..#CE17/18 #CE6..#CE17 0 1 #CE4..
4 PERIPHERAL CIRCUITS A-1 Register name Address Bit G/A read signal 0048138 control register (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BCLK select register Name A18AS A16AS A14AS A12AS – A8AS A6AS A5AS A18RD A16RD A14RD A12RD – A8RD A6RD A5RD 004813A D7–4 – (B) D3 A1X1MD D2 – D1 BCLKSEL1 D0 BCLKSEL0 S1C33L03 PRODUCT PART Function Area 18, 17 address strobe signal Area 16, 15 address strobe signal Area 14, 13 address strobe signal Area 12, 11 address strobe signal reserved Area 8, 7 addre
4 PERIPHERAL CIRCUITS Register name Address Bit Name Function Setting 16-bit timer 0 comparison register A 0048180 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR0A15 CR0A14 CR0A13 CR0A12 CR0A11 CR0A10 CR0A9 CR0A8 CR0A7 CR0A6 CR0A5 CR0A4 CR0A3 CR0A2 CR0A1 CR0A0 16-bit timer 0 comparison data A CR0A15 = MSB CR0A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 0 comparison register B 0048182 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR0B15 CR0B14 CR0B13 C
4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name Function Setting 16-bit timer 1 comparison register A 0048188 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 1 comparison register B 004818A (HW) 16-bit timer 1 counter data register CR1A15 CR1A14 CR1A13 CR1A12 CR1A11 CR1A10 CR1A9 CR1A8 CR1A7 CR1A6 CR1A5 CR1A4 CR1A3 CR1A2 CR1A1 CR1A0 16-bit timer 1 comparison data A CR1A15 = MSB CR1A0 = LSB 0 to 65535 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR1B15 CR1B14 CR1B
4 PERIPHERAL CIRCUITS Register name Address Bit Name Function Setting 16-bit timer 2 comparison register A 0048190 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR2A15 CR2A14 CR2A13 CR2A12 CR2A11 CR2A10 CR2A9 CR2A8 CR2A7 CR2A6 CR2A5 CR2A4 CR2A3 CR2A2 CR2A1 CR2A0 16-bit timer 2 comparison data A CR2A15 = MSB CR2A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 2 comparison register B 0048192 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR2B15 CR2B14 CR2B13 C
4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name Function Setting 16-bit timer 3 comparison register A 0048198 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 3 comparison register B 004819A (HW) 16-bit timer 3 counter data register CR3A15 CR3A14 CR3A13 CR3A12 CR3A11 CR3A10 CR3A9 CR3A8 CR3A7 CR3A6 CR3A5 CR3A4 CR3A3 CR3A2 CR3A1 CR3A0 16-bit timer 3 comparison data A CR3A15 = MSB CR3A0 = LSB 0 to 65535 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR3B15 CR3B14 CR3B
4 PERIPHERAL CIRCUITS Register name Address Bit Name Function Setting 16-bit timer 4 comparison register A 00481A0 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR4A15 CR4A14 CR4A13 CR4A12 CR4A11 CR4A10 CR4A9 CR4A8 CR4A7 CR4A6 CR4A5 CR4A4 CR4A3 CR4A2 CR4A1 CR4A0 16-bit timer 4 comparison data A CR4A15 = MSB CR4A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 4 comparison register B 00481A2 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR4B15 CR4B14 CR4B13 C
4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name Function Setting 16-bit timer 5 comparison register A 00481A8 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 5 comparison register B 00481AA (HW) 16-bit timer 5 counter data register CR5A15 CR5A14 CR5A13 CR5A12 CR5A11 CR5A10 CR5A9 CR5A8 CR5A7 CR5A6 CR5A5 CR5A4 CR5A3 CR5A2 CR5A1 CR5A0 16-bit timer 5 comparison data A CR5A15 = MSB CR5A0 = LSB 0 to 65535 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR5B15 CR5B14 CR5B
4 PERIPHERAL CIRCUITS Register name Address Bit IDMA base address loworder register 0048200 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IDMA base address high-order register 0048202 DF–C – (HW) DB DBASEH11 DA DBASEH10 D9 DBASEH9 D8 DBASEH8 D7 DBASEH7 D6 DBASEH6 D5 DBASEH5 D4 DBASEH4 D3 DBASEH3 D2 DBASEH2 D1 DBASEH1 D0 DBASEH0 reserved IDMA base address high-order 12 bits (Initial value: 0x0C003A0) IDMA start register 0048204 (B) D7 DSTART D6–0 DCHN IDMA start IDMA channel number 1 IDMA
4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name High-speed DMA Ch.0 transfer counter register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC0_L7 TC0_L6 TC0_L5 TC0_L4 TC0_L3 TC0_L2 TC0_L1 TC0_L0 BLKLEN07 BLKLEN06 BLKLEN05 BLKLEN04 BLKLEN03 BLKLEN02 BLKLEN01 BLKLEN00 Ch.0 transfer counter[7:0] (block transfer mode) DF DE DUALM0 D0DIR DD–8 D7 D6 D5 D4 D3 D2 D1 D0 – TC0_H7 TC0_H6 TC0_H5 TC0_H4 TC0_H3 TC0_H2 TC0_H1 TC0_H0 Ch.0 address mode selection D) Invalid S) Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit High-speed 0048228 DMA Ch.0 (HW) low-order destination address set-up register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D0ADRL15 D) Ch.0 destination address[15:0] D0ADRL14 S) Invalid D0ADRL13 D0ADRL12 D0ADRL11 D0ADRL10 D0ADRL9 D0ADRL8 D0ADRL7 D0ADRL6 D0ADRL5 D0ADRL4 D0ADRL3 D0ADRL2 D0ADRL1 D0ADRL0 DF DE D0MOD1 D0MOD0 Ch.0 transfer mode DD DC D0IN1 D0IN0 D) Ch.
4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name High-speed DMA Ch.1 transfer counter register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC1_L7 TC1_L6 TC1_L5 TC1_L4 TC1_L3 TC1_L2 TC1_L1 TC1_L0 BLKLEN17 BLKLEN16 BLKLEN15 BLKLEN14 BLKLEN13 BLKLEN12 BLKLEN11 BLKLEN10 Ch.1 transfer counter[7:0] (block transfer mode) DF DE DUALM1 D1DIR DD–8 D7 D6 D5 D4 D3 D2 D1 D0 – TC1_H7 TC1_H6 TC1_H5 TC1_H4 TC1_H3 TC1_H2 TC1_H1 TC1_H0 Ch.1 address mode selection D) Invalid S) Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit High-speed 0048238 DMA Ch.1 (HW) low-order destination address set-up register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D1ADRL15 D) Ch.1 destination address[15:0] D1ADRL14 S) Invalid D1ADRL13 D1ADRL12 D1ADRL11 D1ADRL10 D1ADRL9 D1ADRL8 D1ADRL7 D1ADRL6 D1ADRL5 D1ADRL4 D1ADRL3 D1ADRL2 D1ADRL1 D1ADRL0 DF DE D1MOD1 D1MOD0 Ch.1 transfer mode DD DC D1IN1 D1IN0 D) Ch.
4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name High-speed DMA Ch.2 transfer counter register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC2_L7 TC2_L6 TC2_L5 TC2_L4 TC2_L3 TC2_L2 TC2_L1 TC2_L0 BLKLEN27 BLKLEN26 BLKLEN25 BLKLEN24 BLKLEN23 BLKLEN22 BLKLEN21 BLKLEN20 Ch.2 transfer counter[7:0] (block transfer mode) DF DE DUALM2 D2DIR DD–8 D7 D6 D5 D4 D3 D2 D1 D0 – TC2_H7 TC2_H6 TC2_H5 TC2_H4 TC2_H3 TC2_H2 TC2_H1 TC2_H0 Ch.2 address mode selection D) Invalid S) Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit High-speed 0048248 DMA Ch.2 (HW) low-order destination address set-up register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D2ADRL15 D) Ch.2 destination address[15:0] D2ADRL14 S) Invalid D2ADRL13 D2ADRL12 D2ADRL11 D2ADRL10 D2ADRL9 D2ADRL8 D2ADRL7 D2ADRL6 D2ADRL5 D2ADRL4 D2ADRL3 D2ADRL2 D2ADRL1 D2ADRL0 DF DE D2MOD1 D2MOD0 Ch.2 transfer mode DD DC D2IN1 D2IN0 D) Ch.
4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name High-speed DMA Ch.3 transfer counter register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC3_L7 TC3_L6 TC3_L5 TC3_L4 TC3_L3 TC3_L2 TC3_L1 TC3_L0 BLKLEN37 BLKLEN36 BLKLEN35 BLKLEN34 BLKLEN33 BLKLEN32 BLKLEN31 BLKLEN30 Ch.3 transfer counter[7:0] (block transfer mode) DF DE DUALM3 D3DIR DD–8 D7 D6 D5 D4 D3 D2 D1 D0 – TC3_H7 TC3_H6 TC3_H5 TC3_H4 TC3_H3 TC3_H2 TC3_H1 TC3_H0 Ch.3 address mode selection D) Invalid S) Ch.
4 PERIPHERAL CIRCUITS Register name Address Bit High-speed 0048258 DMA Ch.3 (HW) low-order destination address set-up register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D3ADRL15 D) Ch.3 destination address[15:0] D3ADRL14 S) Invalid D3ADRL13 D3ADRL12 D3ADRL11 D3ADRL10 D3ADRL9 D3ADRL8 D3ADRL7 D3ADRL6 D3ADRL5 D3ADRL4 D3ADRL3 D3ADRL2 D3ADRL1 D3ADRL0 DF DE D3MOD1 D3MOD0 Ch.3 transfer mode DD DC D3IN1 D3IN0 D) Ch.
4 PERIPHERAL CIRCUITS A-1 Register name Address SDRAM area configuration register 039FFC0 (B) SDRAM 039FFC1 control register (B) Bit Name SDRAR0 SDRAR1 – SDRPC0 SDRPC1 – Area 7/13 configuration Area 8/14 configuration reserved #CE7/13 pin configuration #CE8/14 pin configuration reserved 1 SDRAM 1 SDRAM D7 D6 D5 D4 SDRENA SDRINI SDRSRF SDRIS Enable SDRAM signals Start SDRAM power up Enable SDRAM self-refresh Initial command sequence 1 1 1 1 039FFC2 D7 – (B) D6–5 SDRCA1 SDRCA0 D4 – D3–2 SDRRA1
4 PERIPHERAL CIRCUITS Register name Address SDRAM timing set-up register 2 Bit Name Function 039FFC5 D7–6 SDRTRCD1 SDRAM tRCD spec (B) SDRTRCD0 0 0 0 R/W R/W – – – 0 to 4096 – 1 1 1 1 1 1 1 1 1 1 1 1 – 0 when being read. R/W – 2 to 15 – 1 1 1 1 – 0 when being read. R/W This register must not be set less than "0x02". reserved – 1 8 bits 0 16 bits SDRAM data path bit width SDRAM bank interleaved access 1 Interleaved 0 One bank – reserved – 0 0 – – 0 when being read.
4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name Revision code register D7 D6 D5 D4 D3 D2 D1 D0 PCODE5 PCODE4 PCODE3 PCODE2 PCODE1 PCODE0 RCODE1 RCODE0 LCDC mode register 0 LCDC mode register 1 039FFE0 (B) Revision code 039FFE2 (B) BPP1 BPP0 Bit-per-pixel select (Display mode) – DBLANK FRMRPT – INVDISP reserved Blank display Frame repeat for EL panel reserved Invert display 039FFE3 D7–6 – (B) D5 LCDCEN D4 LPWREN D3–2 – D1 LPSAVE1 D0 LPSAVE0 Init.
4 PERIPHERAL CIRCUITS Register name Address Bit Vertical 039FFEA non-display (B) period register D7 D6 D5 D4 D3 D2 D1 D0 Name VNDPF – VNDP5 VNDP4 VNDP3 VNDP2 VNDP1 VNDP0 Function Setting Vertical non-display period status 1 VNDP 0 Display – reserved Non display period (lines) Vertical non-display period – Init. R/W Remarks 0 – 0 0 0 0 0 0 R – 0 when being read. R/W – 0 0 0 0 0 0 – 0 when being read.
4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name Screen 1 vertical size register 1 039FFF3 D7–2 – (B) D1 S1VSIZE9 D0 S1VSIZE8 FIFO control register 039FFF4 (B) D7 D6 D5 D4 D3 D2 D1 D0 Function Setting reserved Screen 1 vertical size (high-order 2 bits) – reserved FIFOEO3 FIFO empty offset FIFOEO2 FIFOEO1 FIFOEO0 LCLKSEL2 LCDC clock select LCLKSEL1 LCLKSEL0 – 0 0 – 0 when being read. R/W – Fix at 8 (0b1000) – 0 0 0 0 0 0 0 – 0 when being read. R/W – 0 0 0 0 – 0 when being read.
4 PERIPHERAL CIRCUITS Register name Address Bit Name LCDC 039FFFD system control (B) register D7 D6 D5 D4 D3 D2 D1 D0 VRAMAR VRAMWT2 VRAMWT1 VRAMWT0 EDMAEN BREQEN LCDCST LCDCEC A-64 Function Setting VRAM area select 1 Area 8 VRAM wait control (number of wait cycles for SRAM) External DMA enable External bus-request enable A0/BSL select Big/little endian select EPSON 1 1 1 1 Init.
5 POWER-DOWN CONTROL A-1 5 Power-Down Control This chapter describes the controls used to reduce power consumption of the device. Points on power saving The current consumption of the device varies greatly with the CPU's operation mode, the system clocks used, and the peripheral circuits operated.
5 POWER-DOWN CONTROL Function System clock switch over High-speed (OSC3) oscillation ON/OFF control System clock division ratio selection Control bit CLKCHG(D2)/ Power control register(0x40180) SOSC3(D1)/ Power control register(0x40180) CLKDT(D[7:6])/ Power control register(0x40180) "1" "0" Default OSC3 OSC1 OSC3 ON OFF "11" = 1/8 "10" = 1/4 "01" = 1/2 "00" = 1/1 ON 1/1 Turning off the prescaler and peripheral circuits Current consumption can be reduced by turning off the peripheral circuits ope
5 POWER-DOWN CONTROL A-1 The same clock source must be used for the prescaler operating clock and the CPU operating clock. Therefore, when operating the CPU in low-speed with the OSC1 clock, the prescaler input clock must be switched according to the CPU operating clock. In this case, in order to prevent a malfunction in the peripheral circuit, the prescaler should be turned off before switching the CPU operating clock.
6 BASIC EXTERNAL WIRING DIAGRAM 6 Basic External Wiring Diagram FPDAT[7:0] FPSHIFT FPFRAME FPLINE DRDY LCDPWR LCD panel External Bus HSDMA A[23:0] D[15:0] #RD #EMEMRD #DRD #GARD #GAAS #WRL/#WR/#WE #WRH/#BSH #DWE/#SDWE #HCAS/#SDCAS #LCAS/#SDRAS #CExx/#RASx/#SDCEx SDA10 SDCKE HDQM/LDQM #CE10EX #WAIT BCLK S1C33L03 #BUSREQ [The potential of the substrate #BUSACK (back of the chip) is VSS.
7 PRECAUTIONS ON MOUNTING A-1 7 Precautions on Mounting The following shows the precautions when designing the board and mounting the IC. Oscillation Circuit • Oscillation characteristics change depending on conditions (board pattern, components used, etc.). In particular, when a ceramic oscillator or crystal oscillator is used, use the oscillator manufacturer's recommended values for constants such as capacitance and resistance.
7 PRECAUTIONS ON MOUNTING (2) When connecting between the VDD and VSS pins with a bypass capacitor, the pins should be connected as short as possible. Bypass capacitor connection example VDD VDD VSS VSS A/D Converter • When the A/D converter is not used, the power supply pin AVDDE for the analog system should be connected to VDDE.
8 ELECTRICAL CHARACTERISTICS A-1 8 Electrical Characteristics 8.1 Absolute Maximum Rating Item Symbol Supply voltage C33 I/O power voltage Input voltage High-level output current VDD VDDE VI IOH Low-level output current IOL Analog power voltage Analog input voltage Storage temperature AVDDE AVIN TSTG S1C33L03 PRODUCT PART Condition Rated value 1 pin Total of all pins 1 pin Total of all pins -0.3 to +4.0 -0.3 to +7.0 -0.3 to VDDE+0.5 -10 -40 10 40 -0.3 to +7.0 -0.3 to AVDDE+0.
8 ELECTRICAL CHARACTERISTICS 8.2 Recommended Operating Conditions 1) 3.3 V/5.0 V dual power source Item Supply voltage (high voltage) Supply voltage (low voltage) Input voltage CPU operating clock frequency External bus operating clock frequency Low-speed oscillation frequency Operating temperature Input rise time (normal input) Input fall time (normal input) Input rise time (schmitt input) Input fall time (schmitt input) Symbol Condition VDDE VDD HVI LVI fCPU fBUS fOSC1 Ta tri tfi tri tfi Min. Typ.
8 ELECTRICAL CHARACTERISTICS A-1 8.3 DC Characteristics 1) 3.3 V/5.0 V dual power source (Unless otherwise specified: VDDE=5V±0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C) Symbol Condition Min. Typ. Max. Unit ∗ Input leakage current ILI -1 – 1 µA Off-state leakage current IOZ -1 – 1 µA High-level output voltage VOH IOH=-3mA (Type1), IOH=-12mA (Type3), VDDE – – V -0.4 VDDE=Min. Low-level output voltage VOL IOL=3mA (Type1), IOL=12mA (Type3), – – 0.
8 ELECTRICAL CHARACTERISTICS 3) 2.0 V single power source Item (Unless otherwise specified: VDDE=VDD=2V±0.2V, VSS=0V, Ta=-40°C to +85°C) Condition Min. Typ. Max. Unit ∗ Static state, Tj=85°C – – 80 µA -1 – 1 µA -1 – 1 µA IOH=-0.6mA (Type1), IOH=-2mA (Type2), VDD – – V -0.2 IOH=-4mA (Type3), VDD=Min. IOL=0.6mA (Type1), IOL=2mA (Type2), – – 0.
8 ELECTRICAL CHARACTERISTICS A-1 8.4 Current Consumption 1) 3.3 V power source (Unless otherwise specified: VDDE=2.7V to 5.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C) Symbol Condition Min. Typ. Max.
8 ELECTRICAL CHARACTERISTICS 8.5 A/D Converter Characteristics 1) 3.3 V/5.0 V dual power source (Unless otherwise specified: VDDE=AVDDE=4.5V to 5.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C, ST[1:0]=11) Item Symbol Condition Min. Typ. Max.
8 ELECTRICAL CHARACTERISTICS A-1 Zero scale error Digital output (hex) 004 Ideal conversion characteristic 003 002 V[000]h (=0.5LSB) Actual conversion characteristic Zero scale error EZS = 001 (V'[000]h - 0.5LSB') - (V[000]h - 0.5LSB) [LSB] 1LSB V'[000]h 000 VSS A-8 Analog input Full scale error V[3FF]h (=1022.5LSB) V'[3FF]h Digital output (hex) 3FF 3FE Full scale error EFS = 3FD (V'[3FF]h + 0.5LSB') - (V[3FF]h + 0.
8 ELECTRICAL CHARACTERISTICS 8.6 AC Characteristics 8.6.
8 ELECTRICAL CHARACTERISTICS A-1 8.6.3 C33 Block AC Characteristic Tables External clock input characteristics (Note) These AC characteristics apply to input signals from outside the IC. The OSC3 input clock must be within VDD to VSS voltage range. 1) 3.3 V/5.0 V dual power source (Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C) Symbol Min. Max.
8 ELECTRICAL CHARACTERISTICS Common characteristics 1) 3.3 V/5.0 V dual power source (Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C) Symbol Min. Max.
8 ELECTRICAL CHARACTERISTICS A-1 SRAM read cycle 1) 3.3 V/5.0 V dual power source (Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C) Symbol Min. Max. Unit ∗ Read signal delay time (2) tRDD2 8 ns Read signal pulse width tRDW tCYC(0.5+WC)-8 ns Read address access time (1) tACC1 tCYC(1+WC)-20 ns Chip enable access time (1) tCEAC1 tCYC(1+WC)-20 ns Read signal access time (1) tRDAC1 tCYC(0.5+WC)-20 ns Item 2) 3.
8 ELECTRICAL CHARACTERISTICS DRAM access cycle common characteristics 1) 3.3 V/5.0 V dual power source (Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C) Symbol Min. Max. Unit ∗ #RAS signal delay time (1) tRASD1 10 ns #RAS signal delay time (2) tRASD2 10 ns #RAS signal pulse width tRASW tCYC(2+WC)-10 ns #CAS signal delay time (1) tCASD1 10 ns #CAS signal delay time (2) tCASD2 10 ns #CAS signal pulse width tCASW tCYC(0.
8 ELECTRICAL CHARACTERISTICS A-1 DRAM random access cycle and DRAM fast-page cycle 1) 3.3 V/5.0 V dual power source (Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C) Symbol Min. Max. Unit ∗ Column address access time tACCF tCYC(1+WC)-25 ns #RAS access time tRACF tCYC(1.5+WC)-25 ns #CAS access time tCACF tCYC(0.5+WC)-25 ns Item 2) 3.
8 ELECTRICAL CHARACTERISTICS SDRAM access cycle 1) #X2SPD = "1" (CPU : SDRAM clock = 1 : 1), 3.3 V single power source (Unless otherwise specified: VDDE=VDD=3.0V to 3.6V, VSS=0V, Ta=-40°C to +85°C) Symbol Min. Max.
8 ELECTRICAL CHARACTERISTICS A-1 Burst ROM read cycle 1) 3.3 V/5.0 V dual power source (Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C) Symbol Min. Max. Unit ∗ Read address access time (2) tACC2 tCYC(1+WC)-20 ns Chip enable access time (2) tCEAC2 tCYC(1+WC)-20 ns Read signal access time (2) tRDAC2 tCYC(0.5+WC)-20 ns Burst address access time tACCB tCYC(1+WC)-20 ns Item A-8 2) 3.3 V single power source (Unless otherwise specified: VDDE=VDD=2.7V to 3.
8 ELECTRICAL CHARACTERISTICS Input, Output and I/O port 1) 3.3 V/5.0 V dual power source (Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C) Symbol Min. Max. Unit ∗ Input data setup time tINPS 20 ns Input data hold time tINPH 10 ns Output data delay time tOUTD 20 ns K-port interrupt SLEEP, HALT2 mode tKINW 30 ns input pulse width Others 2 × tCYC ns Item 2) 3.3 V single power source (Unless otherwise specified: VDDE=VDD=2.7V to 3.
8 ELECTRICAL CHARACTERISTICS A-1 8.6.
8 ELECTRICAL CHARACTERISTICS SRAM read cycle (basic cycle: 1 cycle) tC3 BCLK ;;;; ;;;; t tAD tAD A[23:0] tCE1 CE2 #CEx tRDD1 tRDD2 tRDW #RD tCEAC1 tACC1 ;;;;;;; ;;;;;;; t tRDAC1 D[15:0] ∗1 tRDH RDS ;;;;;; ;;;;;; #WAIT tWTS tWTH ;;;;;; ;;;;;; *1 tRDH is measured with respect to the first signal change (negation) from among the #RD, #CEx and A[23:0] signals.
8 ELECTRICAL CHARACTERISTICS A-1 SRAM write cycle (basic cycle: 2 cycles) C1 C2 BCLK ;;;; ;;;; t tAD tAD A[23:0] tCE1 CE2 A-8 #CEx tWRD1 tWRD2 tWRW #WR tWDD1 tWDH D[15:0] t ;;;; ;;;; t ;;;;;; ;;;;;; WTS #WAIT WTH SRAM write cycle (when wait cycles are inserted) C1 Cw(wait cycle) Cw(wait cycle) Wait cycle follows Last cycle follows Cn(last cycle) BCLK ;;; ;;; t tAD tAD A[23:0] tCE1 CE2 #CEx tWRD1 tWRD2 tWRW #WR tWDD1 tWDH D[15:0] tWTS #WAIT S1C33L03 PRODUCT PART
8 ELECTRICAL CHARACTERISTICS DRAM random access cycle (basic cycle) Data transfer #1 RAS1 Next data transfer CAS1 PRE1(precharge) RAS1' CAS1' BCLK tAD ;;;;;;;;; ;;;;;;;;; t tAD tAD A[23:0] tRASD1 RASD2 tRASW #RAS tCASD1 tCASD2 tCASW #HCAS/ #LCAS tRDD1 tRDD3 tRDW2 #RD tCACF tRACF tACCF tRDS tRDH ∗1 ;;;;;;;;;; ;;;;;;;;;; t D[15:0] ;;;;; ;;;;; t WRD1 ;;;;;;; ;;;;;;; WRD3 tWRW2 #WE ;;;;; ;;;;; tWDD1 tWDD2 D[15:0] ∗1 tRDH is measured with respect to the first signal change (nega
8 ELECTRICAL CHARACTERISTICS A-1 EDO DRAM random access cycle (basic cycle) Data transfer #1 RAS1 Next data transfer CAS1 PRE1(precharge) RAS1' CAS1' BCLK tAD ;;;;;;;;; ;;;;;;;;; t tAD tAD A[23:0] tRASD1 RASD2 A-8 tRASW #RAS tCASD1 tCASD2 tCASW #HCAS/ #LCAS tRDD1 tRDD3 tRDW2 #RD tCACE tRACE tACCE tRDH ∗1 ;;;;;;;;;; ;;;;;;;;;; tRDS2 D[15:0] tWRD1 ;;; ;;; tWRD3 tWRW2 #WE ;;;;; ;;;;; tWDD1 tWDD2 D[15:0] ∗1 tRDH is measured with respect to the first signal change (negation) of
8 ELECTRICAL CHARACTERISTICS DRAM CAS-before-RAS refresh cycle CBR refresh cycle CCBR1 CCBR2 CCBR3 BCLK ;;;;;;;; ;;;;;;;; #RAS tRASD1 tCASD1 tRASD2 tCASD2 ;;;;;; ;;;;;; #HCAS/ #LCAS #WE ;;;;;;;; ;;;;;;;; ;;;;;; ;;;;;; DRAM self-refresh cycle Self-refresh mode setup Self-refresh mode Self-refresh mode canceration 6-cycle precharge (Fixed) BCLK #RAS ;;;;;;; ;;;;;;; tRASD1 tCASD1 ;;;; ;;;; tRASD2 tCASD2 #HCAS/ #LCAS SDRAM clock (1) #X2SPD = high (CPU clock : SDRAM clock = 1 : 1) OSC3 (Hi
8 ELECTRICAL CHARACTERISTICS A-1 SDRAM access cycle Bank active Read/write nop nop Precharge BCLK SDCKE A[23:0] SDA10 H ;;; t ;;; ;;; t ;;; AD valid (Bank, Row) valid (Column) A10D valid valid tCED1 ;;;;;;;;;;;;; ;;;;;;;;;;;;; ;;;;;;;;;;;;; ;;;;;;;;;;;;; valid valid tCED2 ;;;; ;;;; ;;;; ;;;; A-8 #SDCEx tRASD1 tRASD2 #SDRAS tCASD1 tCASD2 #SDCAS tWED1 tWED2 #SDWE (read) D[15:0] t ;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;; RDS tRDH valid valid tDQMD1 HDQM/ LDQM tWED
8 ELECTRICAL CHARACTERISTICS SDRAM auto-refresh cycle Auto refresh nop nop nop nop BCLK SDCKE A[23:0] SDA10 #SDCEx #SDRAS #SDCAS #SDWE D[15:0] HDQM/ LDQM ∗ H ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; t t ;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;; t t ;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;; t t ;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;; t t ;;;;;
8 ELECTRICAL CHARACTERISTICS A-1 Burst ROM read cycle SRAM read cycle Burst cycle Burst cycle Burst cycle BCLK tAD tAD A[23:2] tAD tAD tAD tAD tAD A[1:0] A-8 tCE1 tCE2 #CEx tRDD1 tRDD2 #RD tACC2 tCEAC tRDAC2 tRDS D[15:0] ;;;;; ;;;;; tACCB tACCB ;;;;; ;;;;; t tACCB ;;;;; ;;;;; t tRDS tRDS RDH RDH ;;;;; ;;;;; t tRDS RDH tRDH∗1 ∗1 tRDH is measured with respect to the first signal change (negation) from among the #RD, #CEx and A[23:0] signals.
8 ELECTRICAL CHARACTERISTICS 8.6.5 LCD Interface AC Characteristics Conditions: VDDE=3.3V±10% or 5.0V±10%, Ta=-40°C to +85°C, CL=60pF (LCD panel interface) Trise and Tfall for all inputs must be less than 5 ns (10%–90%). Power up/down timing LCDCEN bit LPWEREN bit LPSAVE[1:0] bits FP signals 00 11 Inactive Active 00 11 Inactive t1 t4 t2 t3 00 Active Inactive t1 t4 LCDPWR signal Symbol t1 t2 t3 t4 t5 t6 A-96 t6 t5 Parameter t6 Min.
8 ELECTRICAL CHARACTERISTICS A-1 4-bit single monochrome panel timing VDP VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[7:4] Line 1 Line 2 Line 3 Line 4 Line 239 Line 240 Line 1 Line 2 A-8 FPLINE DRDY (MOD) HDP HNDP FPSHIFT FPDAT7 1-1 1-5 1-317 FPDAT6 1-2 1-6 1-318 FPDAT5 1-3 1-7 1-319 FPDAT4 1-4 1-8 1-320 ∗ Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320 × 240 panel For this timing diagram FPSMASK (D2/0x39FFE1) is set to "1" VDP = Vertical Display Period =
8 ELECTRICAL CHARACTERISTICS Sync Timing t1 t2 Frame Pulse t4 t3 Line Pulse t5 DRDY (MOD) Data Timing Line Pulse t6 t8 t7 t9 t14 t11 t10 Shift Pulse t12 FPDAT[7:4] Note: t13 1 2 For this timing diagram FPSMASK (D2/0x39FFE1) is set to "1". 4-bit Single Monochrome Panel AC Timing Symbol Parameter Min.
8 ELECTRICAL CHARACTERISTICS A-1 8-bit single monochrome panel timing VDP VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[7:0] Line 1 Line 2 Line 3 Line 4 Line 479 Line 480 Line 1 Line 2 A-8 FPLINE DRDY (MOD) HDP HNDP FPSHIFT FPDAT7 1-1 1-9 1-633 FPDAT6 1-2 1-10 1-634 FPDAT5 1-3 1-11 1-635 FPDAT4 1-4 1-12 1-636 FPDAT3 1-5 1-13 1-637 FPDAT2 1-6 1-14 1-638 FPDAT1 1-7 1-15 1-639 FPDAT0 1-8 1-16 1-640 ∗ Diagram drawn with 2 FPLINE vertical blank period Example timing for a 64
8 ELECTRICAL CHARACTERISTICS Sync Timing t1 t2 Frame Pulse t4 t3 Line Pulse t5 DRDY (MOD) Data Timing Line Pulse t6 t8 t7 t9 t14 t11 t10 Shift Pulse t12 FPDAT[7:0] Note: t13 1 2 For this timing diagram FPSMASK (D2/0x39FFE1) is set to "1". 8-bit Single Monochrome Panel AC Timing Symbol Parameter Min.
8 ELECTRICAL CHARACTERISTICS A-1 4-bit single color panel timing VDP VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[7:4] Line 1 Line 2 Line 3 Line 4 Line 239 Line 240 Line 1 Line 2 A-8 FPLINE DRDY (MOD) HDP HNDP FPSHIFT FPDAT7 1-R1 1-G2 1-B3 1-B319 FPDAT6 1-G1 1-B2 1-R4 1-R320 FPDAT5 1-B1 1-R3 1-G4 1-G320 FPDAT4 1-R2 1-G3 1-B4 1-B320 ∗ Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320 × 240 panel VDP = Vertical Display Period = LDVSIZE[9:0] + 1 (lines) LDVS
8 ELECTRICAL CHARACTERISTICS Sync Timing t1 t2 Frame Pulse t4 t3 Line Pulse t5 DRDY (MOD) Data Timing Line Pulse t6 t8 t7 t9 t14 t11 t10 Shift Pulse t12 FPDAT[7:4] t13 1 2 4-bit Single Color Panel AC Timing Symbol Parameter Min.
8 ELECTRICAL CHARACTERISTICS A-1 8-bit single color panel timing (Format 1) VDP VNDP FPFRAME FPLINE FPDAT[7:0] Line 1 Line 2 Line 3 Line 4 Line 479 Line 480 Line 1 Line 2 A-8 FPLINE FPSHIFT HDP HNDP FPSHIFT2 FPDAT7 1-R1 1-G1 1-G6 1-B6 1-B11 1-R12 1-R636 FPDAT6 1-B1 1-R2 1-R7 1-G7 1-G12 1-B12 1-B636 FPDAT5 1-G2 1-B2 1-B7 1-R8 1-R13 1-G13 1-G637 FPDAT4 1-R3 1-G3 1-G8 1-B8 1-B13 1-R14 1-R638 FPDAT3 1-B3 1-R4 1-R9 1-G9 1-G14 1-B14 1-B638 FPDAT2 1-G4 1-B4 1-B9 1-R1
8 ELECTRICAL CHARACTERISTICS Sync Timing t1 t2 Frame Pulse t4 t3 Line Pulse Data Timing Line Pulse t6a t6b t8 t7a t9 t14 t11 t10 Shift Pulse 2 t7b Shift Pulse t12 t13 t12 t13 FPDAT[7:0] 1 2 8-bit Single Color Panel AC Timing (Format 1) Symbol Parameter Min.
8 ELECTRICAL CHARACTERISTICS A-1 8-bit single color panel timing (Format 2) VDP VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[7:0] Line 1 Line 2 Line 3 Line 4 Line 479 Line 480 Line 1 Line 2 A-8 FPLINE DRDY (MOD) HDP HNDP FPSHIFT FPDAT7 1-R1 1-B3 1-G6 1-G638 FPDAT6 1-G1 1-R4 1-B6 1-B638 FPDAT5 1-B1 1-G4 1-R7 1-R639 FPDAT4 1-R2 1-B4 1-G7 1-G639 FPDAT3 1-G2 1-R5 1-B7 1-B639 FPDAT2 1-B2 1-G5 1-R8 1-R640 FPDAT1 1-R3 1-B5 1-G8 1-G640 FPDAT0 1-G3 1-R6 1-B8 1-B640 ∗ Diag
8 ELECTRICAL CHARACTERISTICS Sync Timing t1 t2 Frame Pulse t4 t3 Line Pulse t5 DRDY (MOD) Data Timing Line Pulse t6 t8 t7 t9 t14 t11 t10 Shift Pulse t12 FPDAT[7:0] t13 1 2 8-bit Single Color Panel AC Timing (Format 2) Symbol Parameter Min.
8 ELECTRICAL CHARACTERISTICS A-1 8.7 Oscillation Characteristics Oscillation characteristics change depending on conditions (board pattern, components used, etc.). Use the following characteristics as reference values. In particular, when a ceramic or crystal oscillator is used, use the oscillator manufacturer recommended values for constants such as capacitance and resistance. OSC1 crystal oscillation (Unless otherwise specified: crystal=Q11C02RX#1 32.
8 ELECTRICAL CHARACTERISTICS OSC3 ceramic oscillation Item Symbol tSTA3 Oscillation start time (Unless otherwise specified: VSS=0V, Ta=25°C) Min. Typ. Max. Unit ∗ 10MHz ceramic oscillator 10 ms 1 16MHz ceramic oscillator 10 ms 2 20MHz ceramic oscillator 10 ms 3 25MHz ceramic oscillator 5 ms 4 33MHz ceramic oscillator 5 ms 5 Condition ∗ note) No. 1 2 3 4 5 ∗1 Ceramic Recommended constants Power voltage oscillator CG2 (pF) CD2 (pF) Rf2 (MΩ) range (V) CST10.0MTW 30 30 1 1.8 to 2.2 CST16.
9 PACKAGE A-1 9 Package 9.1 Plastic Package QFP20-144pin (Unit: mm) 22±0.4 20±0.1 108 A-9 73 20±0.1 22±0.4 72 109 INDEX 37 144 1 +0.1 36 1.4±0.1 0.2 –0.05 +0.05 0.125–0.025 0° 10° 0.5±0.2 0.1 1.7max 0.5 1 Limit of power consumption The chip temperature of an LSI rises according to power consumption. The chip temperature can be calculated from environment temperature (Ta), thermal package resistance (θ) and power consumption (PD).
10 PAD LAYOUT 10 Pad Layout 10.1 Pad Layout Diagram Die No. 120 115 110 105 100 95 90 85 80 125 75 130 70 135 65 140 X (0, 0) 60 145 5.38 mm Y 55 150 50 155 45 160 1 5 10 15 20 25 30 35 40 5.
10 PAD LAYOUT A-1 10.2 Pad Coordinate (Unit: µm) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pad name P22/TM0 N.C. P23/TM1 N.C. VSS N.C. P24/TM2/#SRDY2 N.C. P25/TM3/#SCLK2 P26/TM4/SOUT2 P27/TM5/SIN2 VDD P07/#SRDY1/#DMAEND3 P06/#SCLK1/#DMAACK3 P05/SOUT1/#DMAEND2 P04/SIN1/#DMAACK2 FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3/GPO6 FPDAT2/GPO5 FPDAT1/GPO4 FPDAT0/GPO3 VDDE DRDY(MOD/FPSHIFT2) FPFRAME FPLINE FPSHIFT N.C.
10 PAD LAYOUT No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 A-112 Pad name A4/SDA3 A5/SDA4 VDDE A6/SDA5 A7/SDA6 A8/SDA7 A9/SDA8 A10/SDA9 A11 VSS A12/SDA11 A13/SDA12 A14/SDBA0 A15/SDBA1 A16 A17 VSS N.C. A18 N.C. A19 N.C. A20 A21 A22 A23 PLLS1 PLLS0 VSS PLLC X 110.0 0.0 -110.0 -220.0 -330.0 -440.0 -550.0 -660.0 -770.0 -880.0 -990.0 -1100.0 -1210.0 -1320.0 -1430.0 -1540.0 -1650.0 -1760.0 -1870.0 -1980.0 -2090.0 -2200.0 -2310.
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS A-1 Appendix A External Device Interface Timings This section shows setup examples for setting timing conditions of the external system interface as a reference material used when configuring a system with external devices. Pay attention to the following precautions when using this material. • The described AC characteristic values of external devices are standard values.
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS A.1 DRAM (70ns) DRAM interface setup examples – 70ns Operating frequency RAS precharge cycle RAS cycle CAS cycle Refresh RAS pulse width Refresh RPC delay 20MHz 25MHz 33MHz 2 2 2 1 1 2 2 2 3 2 2 3 1 1 1 DRAM interface timing – 70ns DRAM interface Parameter Unit: ns Min. Max. tRC tRP tRAS tCAS tASR tRAH tASC tRCD tRAD 130 50 70 20 0 10 0 20 15 – – 10000 10000 – – – – – 7 2 5 2.5 0.5 1.5 0.5 2.0 1.
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS A-1 DRAM: 70ns, CPU: 33MHz, random read/write cycle tRC RAS cycle CAS cycle RAS precharge 2 3 2 ROW #1 COL #1 ;;;;;;;;; ;;;;;;;;; BCLK A[11:0] tRAD tRAH tASC tRAS tASR ROW #2 tRP #RAS tRCD tCAS A-ap #CAS #RD tRAC tOAC tAA tCAC tOFF ;;;;;;;;; ;;;;;;;;; t D[15:0](RD) RD data ;;;; ;;;; WP #WE tDS tDH D[15:0](WR) ;;; ;;; WR data DRAM: 70ns, CPU: 33MHz, page-mode read/write cycle tPC RAS cycle CAS cycle CAS cycle RAS p
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS DRAM: 70ns, CPU: 25/20MHz, random read/write cycle RAS cycle CAS cycle RAS precharge 1 2 2 COL #1 ;;;;;;;;; ;;;;;;;;; BCLK A[11:0] ROW #1 ROW #2 tRAS #RAS #CAS #RD ;;;;; ;;;;; D[15:0](RD) ;; ;; RD data #WE D[15:0](WR) ;;; ;;; WR data DRAM: 70ns, CPU: 25/20MHz, page-mode read/write cycle RAS cycle CAS cycle CAS cycle RAS precharge 1 2 2 2 COL #2 ;;;;;;;;; ;;;;;;;;; BCLK A[11:0] ROW #1 COL #1 tRAS #RAS #CAS #RD ;;;;; ;;
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS A-1 A.2 DRAM (60ns) DRAM interface setup examples – 60ns Operating frequency RAS precharge cycle RAS cycle CAS cycle 20MHz 25MHz 33MHz 1 2 2 1 1 2 2 2 2 Refresh RAS pulse Refresh RPC delay width 2 2 3 1 1 1 DRAM interface timing – 60ns DRAM interface Parameter Unit: ns Min. Max. tRC tRP tRAS tCAS tASR tRAH tASC tRCD tRAD 110 40 60 15 0 10 0 20 15 – – 10000 10000 – – – – – 6 2 4 1.5 0.5 1.5 0.5 2.0 1.
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS DRAM: 60ns, CPU: 33MHz, random read/write cycle tRC RAS cycle CAS cycle RAS precharge 2 2 2 ROW #1 COL #1 ;;;;;;;;; ;;;;;;;;; BCLK A[11:0] tRAD tRAH tASC tRAS tASR ROW #2 tRP #RAS tRCD tCAS #CAS #RD tRAC tOAC tAA tCAC tOFF ;;;;; ;;;;; t D[15:0](RD) RD data ;;;; ;;;; WP #WE tDS D[15:0](WR) tDH WR data ;;; ;;; DRAM: 60ns, CPU: 33MHz, page-mode read/write cycle tPC RAS cycle CAS cycle CAS cycle RAS precharge 2 2 2 2
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS A-1 DRAM: 60ns, CPU: 25MHz, random read/write cycle RAS cycle CAS cycle RAS precharge 1 2 2 COL #1 ;;;;;;;;; ;;;;;;;;; BCLK A[11:0] ROW #1 ROW #2 tRAS #RAS #CAS #RD ;;;;; ;;;;; D[15:0](RD) ;; ;; RD data #WE D[15:0](WR) A-ap ;;; ;;; WR data DRAM: 60ns, CPU: 25MHz, page-mode read/write cycle RAS cycle CAS cycle CAS cycle RAS precharge 1 2 2 2 COL #2 ;;;;;;;;; ;;;;;;;;; BCLK A[11:0] ROW #1 COL #1 tRAS #RAS #CAS #RD ;;;
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS DRAM: 60ns, CPU: 20MHz, random read/write cycle RAS cycle CAS cycle RAS precharge 1 2 1 COL #1 ;;;;; ;;;;; BCLK A[11:0] ROW #1 ROW #2 tRAS #RAS #CAS #RD ;;;;; ;;;;; D[15:0](RD) ;; ;; RD data #WE D[15:0](WR) ;;; ;;; WR data DRAM: 60ns, CPU: 20MHz, page-mode read/write cycle RAS cycle CAS cycle CAS cycle RAS precharge 1 2 2 1 BCLK A[11:0] ROW #1 COL #1 ;;;;;; ;;;;;; COL #2 tRAS #RAS #CAS #RD ;;;;; ;;;;; D[15:0](RD) RD
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS A-1 A.3 ROM and Burst ROM Burst ROM and mask ROM interface setup examples Operating frequency Normal read cycle Wait cycle Read cycle 20MHz 25MHz 33MHz 2 3 4 Burst read cycle Wait cycle Read cycle 3 4 5 1 1 2 Output disable delay cycle 2 2 3 1.5 1.5 1.
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS ROM: 100ns, CPU: 25MHz, normal read BCLK ;;;;; ;;;;; A[23:0] #CE9, 10 #RD ;;;;;;;;;;; ;;;;;;;;;;; D[15:0] ;;;; ;;;; RD data ROM: 100ns, CPU: 25MHz, burst read BCLK Normal read cycle Burst read cycle ;;; ;;; A[23:0] #CE9, 10 #RD ;;;;;; ;;;;;; ;;; ;;; ;;; ;;; ;;; ;;; RD data D[15:0] RD data RD data RD data ;;; ;;; ROM: 100ns, CPU: 20MHz, normal read BCLK ;;;;; ;;;;; A[23:0] #CE9, 10 #RD D[15:0] ;;;;;;; ;;;;;;; ;;;; ;;;; RD data R
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS A-1 A.4 SRAM (55ns) SRAM interface setup examples – 55ns Operating frequency Read cycle Wait cycle Read cycle 20MHz 25MHz 33MHz 1 2 2 Write cycle Output disable delay cycle 2 3 3 1.5 1.5 1.5 2 3 3 SRAM interface timing – 55ns SRAM interface Parameter Symbol 33MHz Cycle Time 25MHz Cycle Time 20MHz Cycle Time Min. Max. tRC tACC tACS tOE tOHZ 55 – – – 0 – 55 55 30 30 3 3 3 2.5 1.5 90 90 90 75 45 3 3 3 2.5 1.
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS SRAM: 55ns, CPU: 20MHz, read cycle BCLK ;;;;; ;;;;; A[23:0] #CEx #RD ;;;;; ;;;;; RD data D[15:0] ;;;; ;;;; SRAM: 55ns, CPU: 20MHz, write cycle BCLK ;;;;; ;;;;; A[23:0] #CEx #WR D[15:0] A-124 WR data EPSON ;;; ;;; S1C33L03 PRODUCT PART
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS A-1 A.5 SRAM (70ns) SRAM interface setup examples – 70ns Operating frequency Read cycle Wait cycle Read cycle 20MHz 25MHz 33MHz 2 2 3 Write cycle Output disable delay cycle 3 3 4 1.5 1.5 1.5 3 3 4 SRAM interface timing – 70ns SRAM interface Parameter Symbol 33MHz Cycle Time 25MHz Cycle Time 20MHz Cycle Time Min. Max. tRC tACC tACS tOE tOHZ 70 – – – 0 – 70 70 40 30 4 4 4 3.5 1.5 120 120 120 105 45 3 3 3 2.5 1.
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS SRAM: 70ns, CPU: 25/20MHz, read cycle BCLK ;;;;; ;;;;; A[23:0] #CEx #RD ;;;;;;;;; ;;;;;;;;; RD data D[15:0] ;;;; ;;;; SRAM: 70ns, CPU: 25/20MHz, write cycle BCLK ;;;;; ;;;;; A[23:0] #CEx #WR D[15:0] A-126 WR data EPSON ;;; ;;; S1C33L03 PRODUCT PART
APPENDIX A EXTERNAL DEVICE INTERFACE TIMINGS A-1 A.6 8255A 8255A interface setup examples Operating frequency Read cycle Wait cycle Read cycle 9 ∗1 11 14 20MHz 25MHz 33MHz Write cycle 10 12 15 Output disable delay cycle 10 12 15 3.5 3.5 3.5 ∗2 8255A interface timing SRAM interface Parameter Symbol Min. Max. 33MHz Cycle Time 25MHz Cycle Time 20MHz Cycle Time tRC tACC tACS tOE tOHZ 300 – – – 10 – 250 250 250 150 15 15 15 14.5 3.5 450 450 450 435 105 12 12 12 11.5 3.
APPENDIX B PIN CHARACTERISTICS Appendix B Pin Characteristics Pin No.
APPENDIX B PIN CHARACTERISTICS Pin No.
APPENDIX B PIN CHARACTERISTICS Pin No.
S1C33L03 FUNCTION PART
S1C33L03 FUNCTION PART I OUTLINE
I OUTLINE: INTRODUCTION A-1 I-1 INTRODUCTION The Function Part gives a detailed description of the various function blocks built into the Seiko Epson original 32-bit microcomputer S1C33L03. The S1C33L03 employs a RISC type CPU, and has a powerful instruction set capable of compilation into compact code, despite the small CPU core size.
I OUTLINE: INTRODUCTION THIS PAGE IS BLANK.
I OUTLINE: BLOCK DIAGRAM A-1 I-2 BLOCK DIAGRAM The S1C33L03 consists of seven major blocks: C33 Core Block, C33 Peripheral Block, C33 Analog Block, C33 DMA Block, C33 SDRAM Controller Block, C33 LCD Controller Block and C33 Internal Memory Block. Figure 2.1 shows the configuration of the S1C33 blocks.
I OUTLINE: BLOCK DIAGRAM C33 Core Block The C33 Core Block consists of a functional block C33_CORE including CPU, BCU (Bus Control Unit), ITC (Interrupt Controller), CLG (Clock Generator) and DBG (Debug Unit), an I/O pad block for external interface, and an SBUS (Internal Silicon Integration Bus) for interfacing with on-chip Peripheral Macro Cells. The C33 Core Block employs the S1C33000 32-bit RISC type CPU as the core CPU.
I OUTLINE: LIST OF PINS A-1 I-3 LIST OF PINS List of External I/O Pins The following lists the external I/O pins of the C33 Core Block, Peripheral Block and LCD Controller Block. Note that some pins are listed in two or more tables. Table 3.1 List of Pins for External Bus Interface Signals Pin name A0 #BSL A[10:1] SDA[9:0] A11 A[13:12] SDA[12:11] A[15:14] SDBA[1:0] A[23:16] D[15:0] #CE10EX #CE9&10EX #CE9 #CE17 #CE17&18 #CE8 #RAS1 #CE14 #RAS3 #SDCE1 Pin No.
I OUTLINE: LIST OF PINS Pin No.
I OUTLINE: LIST OF PINS A-1 Table 3.2 List of Pins for HSDMA Control Signals Pin name K50 #DMAREQ0 K51 #DMAREQ1 K53 #DMAREQ2 K54 #DMAREQ3 P32 #DMAACK0 #SRDY3 HDQM Pin No.
I OUTLINE: LIST OF PINS Table 3.3 List of Pins for Internal Peripheral Circuits Pin name K50 #DMAREQ0 K51 #DMAREQ1 K52 #ADTRG K53 #DMAREQ2 K54 #DMAREQ3 K60 AD0 K61 AD1 K62 AD2 K63 AD3 K64 AD4 K65 AD5 K66 AD6 K67 AD7 P00 SIN0 P01 SOUT0 P02 #SCLK0 P03 #SRDY0 P04 SIN1 #DMAACK2 Pin No.
I OUTLINE: LIST OF PINS Pin name Pin No.
I OUTLINE: LIST OF PINS Pin No. I/O Pull-up P26 TM4 SOUT2 Pin name 6 I/O – P27 TM5 SIN2 7 I/O – P30 #WAIT #CE4&5 75 I/O – P31 #BUSGET #GARD GPIO2 74 I/O – P32 #DMAACK0 #SRDY3 HDQM 73 I/O – P33 #DMAACK1 SIN3 SDA10 72 I/O – P34 #BUSREQ #CE6 GPIO0 71 I/O – P35 #BUSACK GPIO1 70 I/O – B-I-3-6 Function P26: TM4: SOUT2: I/O port when CFP26(D6/0x402D8) = "0" (default) 16-bit timer 4 output when CFP26(D6/0x402D8) = "1" Serial I/F Ch.
I OUTLINE: LIST OF PINS A-1 Table 3.4 List of Pins for LCD Controller Pin No. I/O Pull-up FPDAT[7:4] Pin name 13–16 O – FPDAT[3:0] GPO[6:3] FPFRAME FPLINE FPSHIFT DRDY(MOD) (FPSHIFT2) LCDPWR 17–20 O – 23 24 25 22 O O O O – – – – 26 O – Pin name Pin No. I/O Pull-up 68 67 129 128 112,113 I O I O I – – – – – 115 – – Pin No.
I OUTLINE: LIST OF PINS THIS PAGE IS BLANK.
S1C33L03 FUNCTION PART II CORE BLOCK
II CORE BLOCK: INTRODUCTION A-1 II-1 INTRODUCTION The core block consists of a functional block C33_CORE including CPU, BCU (Bus Control Unit), ITC (Interrupt Controller), CLG (Clock Generator) and DBG (Debug Unit), an I/O pad block for external interface, and an SBUS (Internal Silicon Integration Bus) for interfacing with on-chip Peripheral Macro Cells.
II CORE BLOCK: INTRODUCTION THIS PAGE IS BLANK.
II CORE BLOCK: CPU AND OPERATING MODE A-1 II-2 CPU AND OPERATING MODE CPU The C33 Core Block employs the S1C33000 32-bit RISC type CPU as the core CPU. Since it has a built-in multiplier, all instructions (105 instructions) in the S1C33000 instruction set including the MAC (multiplication and accumulation) instruction and the multiplication/division instructions are available. All the internal registers of the S1C33000 can be used. The CPU registers and CPU address bus can handle 28-bit addresses.
II CORE BLOCK: CPU AND OPERATING MODE Standby Mode The CPU supports three standby modes: two HALT modes and a SLEEP mode. By setting the CPU in the standby mode, power consumption can greatly be reduced. HALT Mode When the CPU executes the halt instruction, it suspends the program execution and enters the HALT mode. The CPU supports two types of HALT modes (basic HALT mode and HALT2 mode) and either can be selected using the HLT2OP (D3) / Clock option register (0x40190).
II CORE BLOCK: CPU AND OPERATING MODE A-1 Notes on Standby Mode Interrupts The standby mode can be canceled by an interrupt. Therefore, it is necessary to enable the interrupt to be used for canceling the standby mode before setting the CPU in the standby mode. It is also necessary to set the IE (interrupt enable) and IL (interrupt level) bits in the PSR to a condition that can accept the interrupt. Otherwise, the standby mode cannot be canceled even when an interrupt occurs.
II CORE BLOCK: CPU AND OPERATING MODE Trap Table Table 2.1 shows the trap table in the C33 Core. Refer to the "S1C33000 Core CPU Manual" for details of exceptions and Section II-5 in this manual, "ITC (Interrupt Controller)", for interrupts. Serial interface Ch.2 and Ch.3 interrupts share the trap table for port input interrupts and 16-bit timer interrupts. Refer to Section III-8, "Serial Interface", for details of the settings. Table 2.1 Trap Table HEX No.
II CORE BLOCK: CPU AND OPERATING MODE HEX No. 38 39 3A Vector number (Hex address) 40 41 56(Base+E0) 57(Base+E4) 58(Base+E8) 59 60(Base+F0) 61(Base+F4) 62(Base+F8) 63 64(Base+100) 65(Base+104) 44 45 46 47 66–67 68(Base+110) 69(Base+114) 70(Base+118) 71(Base+11C) 3C 3D 3E Exception/interrupt name Serial interface Ch.0 reserved Serial interface Ch.
II CORE BLOCK: CPU AND OPERATING MODE THIS PAGE IS BLANK.
II CORE BLOCK: INITIAL RESET A-1 II-3 INITIAL RESET Pins for Initial Reset Table 3.1 shows the pins used for initial reset. Table 3.1 Pins for Initial Reset Pin name I/O #RESET I #NMI I Function Initial reset input pin (Low active) Low: Resets the CPU. NMI request input pin This pin is also used for selecting a reset method. High: Cold start Low: Hot start The chip is reset when the #RESET pin goes low and starts operating at the rising edge of the reset signal.
II CORE BLOCK: INITIAL RESET Power-on Reset Be sure to reset (cold start) the chip after turning on the power to start operating. Since the #RESET pin is directly connected to an input gate, a power-on reset circuit should be configured outside the chip. An initial reset (#RESET = low) turns the high-speed (OSC3) oscillation circuit on. The CPU starts operating with the OSC3 clock at the rising edge of the reset signal. The high-speed (OSC3) oscillation circuit takes time (10 ms max.
II CORE BLOCK: INITIAL RESET A-1 Boot Address When the core CPU is initially reset, it reads the reset vector (program start address) from the boot address (0x0C00000) and loads the vector to the PC (program counter). Then the CPU starts executing the program from the address when the #RESET pin goes high. The trap table in which trap vectors for interrupts and other trap factors are written also begins from the boot address by the default setting.
II CORE BLOCK: INITIAL RESET THIS PAGE IS BLANK.
II CORE BLOCK: BCU (Bus Control Unit) A-1 II-4 BCU (Bus Control Unit) The BCU (Bus Control Unit) provides an interface for external devices and on-chip user logic block. The types and sizes of memory and peripheral I/O devices can be set for each area of the memory map and can be controlled directly by the BCU. This unit also supports a direct interface for DRAM and burst ROM. This chapter describes how to control the external and internal system interface, and how it operates.
II CORE BLOCK: BCU (Bus Control Unit) User interface signals Table 4.
II CORE BLOCK: BCU (Bus Control Unit) A-1 Combination of System Bus Control Signals The bus control signal pins that have two or more functions have their functionality determined when an interface method is selected by a program. The BCU contains an ordinary external system interface (two interface method are supported) and a DRAM interface. Table 4.
II CORE BLOCK: BCU (Bus Control Unit) Memory Area Memory Map Figure 4.1 shows the memory map supported by the BCU.
II CORE BLOCK: BCU (Bus Control Unit) A-1 External Memory Map and Chip Enable The BCU has a 24-bit external address bus (A[23:0]) and a 16-bit external data bus (D[15:0]), allowing an address space of up to 16 MB to be accessed with one chip enable signal. By default, the address space is divided into 11 areas (areas 0 to 10) for management purposes. Of these, areas 4 to 10 are open to an external system, each provided with an independent chip-enable pin (#CE[10:4]).
II CORE BLOCK: BCU (Bus Control Unit) Area Area 17–18 (#CE17+18) SRAM type 8 or 16 bits Areas 15–16 (#CE15+16) SRAM type 8 or 16 bits Area 14 (#CE14/#RAS3) SRAM type DRAM type 8 or 16 bits Area 13 (#CE13/#RAS2) SRAM type DRAM type 8 or 16 bits Areas 11–12 (#CE11+12) SRAM type 8 or 16 bits Areas 9–10 (#CE9+10EX) SRAM type Burst ROM type 8 or 16 bits Areas 7–8 (#CE7+8) SRAM type 8 or 16 bits Address 0xFFFFFFF 0xD000000 0xCFFFFFF 0xC000000 0xBFFFFFF 0x9000000 0x8FFFFFF 0x8000000 0x7FFFFFF 0x7000000 0x6FFFF
II CORE BLOCK: BCU (Bus Control Unit) A-1 Using Internal Memory on External Memory Area The BCU allows using of an internal memory in the external memory areas. The AxxIO bit in the access control register (0x48132) is used to select either internal access or external access. When "1" is written, the internal device will be accessed and when "0" is written, the external device is accessed (external access by default).
II CORE BLOCK: BCU (Bus Control Unit) Area 10 Area 10 is an external memory area that includes the boot address (0xC00000). This area supports two boot modes. Note: Internal ROM is not provided in the S1C33L03. Area 10 boot mode The boot mode can be configured using the external pins EA10MD[1:0]. Table 4.6 Area 10 Boot Mode Selection EA10MD[1:0] pins 10 11 Area 10 boot mode Internal ROM boot mode External ROM boot mode Internal ROM boot mode The CPU boots by the internal ROM mapped to area 10.
II CORE BLOCK: BCU (Bus Control Unit) A-1 Area 10 memory map Figure 4.4 shows the memory map of area 10. External ROM boot mode 0x0FFFFFF Other modes 0x0FFFFFF Area 10 Area 10 External memory is accessed. External memory is accessed. Set-up example 25 MHz 5 wait Set-up example 25 MHz 5 wait Internal or emulation memory is accessed.
II CORE BLOCK: BCU (Bus Control Unit) Setting External Bus Conditions The type, size, and wait conditions of a device connected to the external bus can be individually set for each area using the control register (0x48120 to 0x48130). The following explains the available setup conditions individually for each area. For details on how to set the DRAM interface conditions, refer to "DRAM Direct Interface". The control register used to set bus conditions is initialized at cold start.
II CORE BLOCK: BCU (Bus Control Unit) A-1 Setting SRAM Timing Conditions The areas set for the SRAM allow wait cycles and output disable delay time to be set. Number of wait cycles: 0 to 7 (incremented in units of one cycle) Output disable delay time: 0.5, 1.5, 2.5, 3.5 cycles This selection can be made once every two areas except for area 6. Table 4.
II CORE BLOCK: BCU (Bus Control Unit) Output disable delay time In cases when a device having a long output disable time is connected, if a read cycle for that device is followed by the next access, contention for the data bus may occur. (Due to the fact the read device's data bus is not placed in the high-impedance state.) The output disable delay time is provided to prevent such data bus contention.
II CORE BLOCK: BCU (Bus Control Unit) A-1 Bus Operation Data Arrangement in Memory The S1C33 Family of devices handle data in bytes (8 bits), half-words (16 bits), and words (32 bits). When accessing data in memory, it is necessary to specify a boundary address that conforms to the data size involved. Specification of an invalid address causes an address error exception. For instructions (e.g.
II CORE BLOCK: BCU (Bus Control Unit) For information on memory connection, see Figure 4.18. Little-endian 31 Byte 3 Source (general-purpose register) Byte 2 Byte 1 Byte 0 2 15 1 0 15 A[1:0]=10 Bus operation 0 0 A[1:0]=00 No. A1 A0 #WRH #WRL 15 Data bus 1 Byte 1 Byte 0 0 0 0 0 2 Byte 3 Byte 2 0 0 0 1 0 Destination (16-bit device) Big-endian 31 Byte 3 Source (general-purpose register) Byte 2 Byte 1 Byte 0 1 15 2 0 15 A[1:0]=00 Bus operation 0 0 A[1:0]=10 No.
II CORE BLOCK: BCU (Bus Control Unit) A-1 Little-endian 31 Byte 3 Source (general-purpose register) Byte 2 Byte 1 Byte 0 1 15 A[1:0]=∗1 1' 0 Bus operation 0 No. A1 A0 #WRH #WRL 15 Data bus 0 1 Byte 0 Data retained 1 0 1 ∗ Data retained Byte 0 1' 0 1 0 ∗ A[1:0]=∗0 Destination (16-bit device) Big-endian 31 Byte 3 Source (general-purpose register) Byte 2 Byte 1 Byte 0 1 15 A[1:0]=∗0 1' 0 Bus operation 0 No.
II CORE BLOCK: BCU (Bus Control Unit) Little-endian 31 Byte 3 Source (general-purpose register) Byte 2 Byte 1 Byte 0 8 2 0 8 A[1:0]=∗1 Bus operation 0 1 0 A[1:0]=∗0 Data bus No. A1 A0 #WRH #WRL 15 1 ∗ 0 Data retained Byte 0 0 X 2 ∗ 1 Data retained Byte 1 0 X 0 (X: Not connected/Unused) Destination (8-bit device) Big-endian 31 Byte 3 Source (general-purpose register) Byte 2 Byte 1 Byte 0 8 1 0 8 A[1:0]=∗0 2 0 Bus operation 0 No.
II CORE BLOCK: BCU (Bus Control Unit) A-1 Bus Clock The bus clock is generated by the BCU using the CPU system clock output from the clock generator. Figure 4.17 shows the clock system.
II CORE BLOCK: BCU (Bus Control Unit) Since the bus clock is generated from the CPU system clock (CPU_CLK), the following settings affect the bus clock: 1. Selection of an oscillation circuit (OSC3 or OSC1) 2. PLL configuration (OSC3_CLK x 1, x2 or x4) 3. CPU clock division ratio for power saving (1/8, 1/4, 1/2, or 1/1 of OSC3_CLK or PLL_CLK) Items 2 and 3 apply when the high-speed (OSC3) oscillation circuit is selected as the CPU clock source.
II CORE BLOCK: BCU (Bus Control Unit) A-1 Bus Cycles in External System Interface The following shows a sample SRAM connection the basic bus cycles.
II CORE BLOCK: BCU (Bus Control Unit) The above example shows a read cycle when a wait mode is inserted via the #WAIT signal. A wait mode consisting of 0 to 7 cycles can also be inserted using the wait control bits. The settings of these bits can also be used in combination with the #WAIT signal. In this case as well, the #WAIT signal is sampled at the falling edge of the transition of BCLK.
II CORE BLOCK: BCU (Bus Control Unit) A-1 SRAM Write Cycles Basic write cycle with no wait mode C1 C2 BCLK ;;; ;;; addr A[23:0] #CExx data D[15:0] #WRH/#WRL #WAIT #WR #BSL/#BSH B-II Figure 4.22 Half-word Write Cycle with No Wait C1 C2 C3 C4 BCLK ;;; ;;; addr A[23:0] #CExx BCU #WRH #WRL D[15:8] Undefined Valid D[7:0] Valid Undefined Figure 4.
II CORE BLOCK: BCU (Bus Control Unit) Write cycle with wait mode Example: When the BCU has no internal wait mode, and 1 wait cycle is inserted via the #WAIT pin C1 CW C2 BCLK ;;; ;;; addr A[23:0] #CExx data D[15:0] #WRH/#WRL #WAIT #WR #BSL/#BSH Figure 4.
II CORE BLOCK: BCU (Bus Control Unit) A-1 Burst ROM Read Cycles Burst read cycle Example: When 4-consecutive-burst and 2-wait cycles are set during the first access BCLK addr[23:2] A[23:2] "00" A[1:0] #CE10(9) D[15:0] #RD "01" "10" "11" ;;;;;;;;;;;;;; ;;;; ;;;; ;;;; ;;;;;;;;;;;;;; ;;;; ;;;; ;;;; IR0 IR1 IR2 ;;; ;;; ;;; ;;; IR3 Figure 4.
II CORE BLOCK: BCU (Bus Control Unit) DRAM Direct Interface Outline of DRAM Interface The BCU incorporates a DRAM direct interface that allows DRAM to be connected directly to areas 8 and 7 or areas 14 and 13. This interface supports the 2CAS method, so that column addresses can be set at between 8 and 11 bits. In addition, this interface supports a fast-page or an EDO-page mode (EDO DRAM directly connectable to areas) as well as random cycles.
II CORE BLOCK: BCU (Bus Control Unit) A-1 DRAM Setting Conditions The DRAM interface allows the following conditions to be selected. Although DRAM can be used in areas 8 and 7 or areas 14 and 13, these condition are applied to all four areas and cannot be set individually for each area. Table 4.
II CORE BLOCK: BCU (Bus Control Unit) Column address size When accessing DRAM, addresses are divided into a row address and a column address as they are output. Choose the size of this column address using RCA, as shown below. Table 4.18 Column Address Size RCA1 RCA0 Column address size 1 1 0 0 1 0 1 0 11 10 9 8 The initial default size is 8 bits. Choose the desired size according to the address input pins of the DRAM to be used.
II CORE BLOCK: BCU (Bus Control Unit) A-1 Refresh RPC delay Use RPC0 to set the RPC delay value of a refresh cycle (a delay time from the immediately preceding precharge to the fall of #CAS). RPC0 = "1": 2 cycles RPC0 = "0": 1 cycle Refresh RAS pulse width Use RRA to set the #RAS pulse width of a CAS-before-RAS refresh cycle. Table 4.19 Refresh RAS Pulse Width RRA1 RRA0 Pulse width 1 1 0 0 1 0 1 0 5 cycles 4 cycles 3 cycles 2 cycles The initial default value is 2 cycles.
II CORE BLOCK: BCU (Bus Control Unit) DRAM Read/Write Cycles The following shows the basic bus cycles of DRAM. The DRAM interface does not accept wait cycles inserted via the #WAIT pin. DRAM random read cycle Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle RAS cycle Precharge cycle CAS cycle BCLK A[11:0] ROW ;;;;;;; ;;;;;;; COL #RASx #HCAS/ #LCAS #RD D[15:0] ;;;;;;;;;;;;; ;;;;;;;;;;;;; data Figure 4.
II CORE BLOCK: BCU (Bus Control Unit) A-1 DRAM random write cycle Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle RAS cycle BCLK A[11:0] Precharge cycle CAS cycle ROW COL #RASx ;;;;;;; ;;;;;;; #HCAS/ #LCAS #WE write data D[15:0] ;;;;; ;;;;; Figure 4.
II CORE BLOCK: BCU (Bus Control Unit) Operation in successive RAS mode Example: RAS: 2 cycles; CAS: 1 cycle; Precharge: 2 cycles (1) RAS cycle CAS cycles in page mode (2) (3) Deassert cycle Assert cycle (4) CAS cycles in page mode Precharge cycle RAS cycle CAS cycles BCLK A[11:0] #RASx #HCAS/ #LCAS #DRD #DWE Accsess to other device than DRAM Not asserted for areas other than DRAM Figure 4.
II CORE BLOCK: BCU (Bus Control Unit) A-1 DRAM Refresh Cycles The DRAM interface supports a CAS-before-RAS refresh cycle and a self-refresh cycle. CAS-before-RAS refresh cycle Before performing a CAS-before-RAS refresh, set RPC2 to "1" while RPC1 = "0" in order to enable the DRAM refresh function. Once this is done, the BCU executes a CAS-before-RAS refresh by using the underflow signal that is output by the 8-bit programmable timer 0 as a trigger.
II CORE BLOCK: BCU (Bus Control Unit) Normally, DRAM specifications require that the contents of all row addresses be refreshed within a certain time before and after a self-refresh. To meet this requirement, make sure a CAS-before-RAS refresh is executed by a program. In this case, set the 8-bit programmable timer 0 so that the contents of all row addresses are refreshed within a predetermined time.
II CORE BLOCK: BCU (Bus Control Unit) A-1 DRAM refresh when bus ownership control is released In systems where DRAM is connected directly, a refresh request could arise while control of the bus ownership is released from the CPU. In such a case, take one of the corrective measures described below. • Monitoring the output signal of the 8-bit programmable timer 0 The underflow signal (DRAM refresh request) of the 8-bit programmable timer 0 can be output from the P10 I/O port pin.
II CORE BLOCK: BCU (Bus Control Unit) I/O Memory of BCU Table 4.23 shows the control bits of the BCU. These I/O memories are mapped into the area (0x48000 and following addresses) used for the internal 16-bit peripheral circuits. However, these I/O memories can be accessed in bytes or words, as well as in half-words.
II CORE BLOCK: BCU (Bus Control Unit) A-1 Register name Address Bit Areas 12–11 0048124 set-up register (HW) DF–7 D6 D5 D4 – A12SZ A12DF1 A12DF0 D3 D2 D1 D0 – A12WT2 A12WT1 A12WT0 DF DE DD DC – A10IR2 A10IR1 A10IR0 Areas 10–9 0048126 set-up register (HW) Areas 8–7 0048128 set-up register (HW) Name Function Init. R/W Remarks reserved – Areas 12–11 device size selection 1 8 bits 0 16 bits Areas 12–11 A18DF[1:0] Number of cycles 1 1 3.5 output disable delay time 1 0 2.5 0 1 1.5 0 0 0.
II CORE BLOCK: BCU (Bus Control Unit) Register name Address Bit Name Areas 6–4 004812A DF–E – set-up register (HW) DD A6DF1 DC A6DF0 Bus control register B-II-4-36 004812E (HW) Function reserved Area 6 output disable delay time DB DA D9 D8 – A6WT2 A6WT1 A6WT0 reserved Area 6 wait control D7 D6 D5 D4 – A5SZ A5DF1 A5DF0 reserved Areas 5–4 device size selection Areas 5–4 output disable delay time D3 D2 D1 D0 – A5WT2 A5WT1 A5WT0 reserved Areas 5–4 wait control DF DE DD DC DB DA RBCLK – RBST8
II CORE BLOCK: BCU (Bus Control Unit) A-1 Register name Address Bit Name Function DRAM timing 0048130 DF–C – reserved set-up register (HW) DB A3EEN Area 3 emulation DA CEFUNC1 #CE pin function selection D9 CEFUNC0 Access control 0048132 register (HW) G/A read signal 0048138 control register (HW) BCLK select register D8 D7 D6 CRAS RPRC1 RPRC0 Successive RAS mode setup DRAM RAS precharge cycles selection D5 D4 D3 – CASC1 CASC0 reserved DRAM CAS cycles selection D2 D1 D0 – RASC1 RASC0 reserved
II CORE BLOCK: BCU (Bus Control Unit) A18SZ: Areas 18–17 device size selection (DE) / Areas 18–15 set-up register (0x48120) A16SZ: Areas 16–15 device size selection (D6) / Areas 18–15 set-up register (0x48120) A14SZ: Areas 14–13 device size selection (D6) / Areas 14–13 set-up register (0x48122) A12SZ: Areas 12–11 device size selection (D6) / Areas 12–11 set-up register (0x48124) A10SZ: Areas 10–9 device size selection (D6) / Areas 10–9 set-up register (0x48126) A8SZ: Areas 8–7 device size selection (D6) /
II CORE BLOCK: BCU (Bus Control Unit) A-1 A14DRA: Area 14 DRAM selection (D8) / Areas 14–13 set-up register (0x48122) A13DRA: Area 13 DRAM selection (D7) / Areas 14–13 set-up register (0x48122) A8DRA: Area 8 DRAM selection (D8) / Areas 8–7 set-up register (0x48128) A7DRA: Area 7 DRAM selection (D7) / Areas 8–7 set-up register (0x48128) Select the DRAM direct interface.
II CORE BLOCK: BCU (Bus Control Unit) A10DRA: Area 10 burst ROM selection (D8) / Areas 10–9 set-up register (0x48126) A9DRA: Area 9 burst ROM selection (D7) / Areas 10–9 set-up register (0x48126) Set areas 10 and 9 for use of burst ROM. Write "1": Burst ROM is used Write "0": Burst ROM is not used Read: Valid When using burst ROM, write "1" to the control bit. The ordinary SRAM interface is selected by writing "0" to the bit. Area 9 can only be used when the CEFUNC = "00".
II CORE BLOCK: BCU (Bus Control Unit) A-1 RCA1–RCA0: Column address size selection (D[B:A]) / Bus control register (0x4812E) Select the column address size of DRAM. Table 4.26 Column Address Size RCA1 RCA0 Column address size 1 1 0 0 1 0 1 0 11 10 9 8 The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. RCA can be read to obtain its set value. At cold start, RCA is set to "0" (8 bits). At hot start, RCA retain its status before being initialized.
II CORE BLOCK: BCU (Bus Control Unit) RRA1–RRA0: Refresh RAS pulse width selection (D[6:5]) / Bus control register (0x4812E) Select the RAS pulse width of a CAS-before-RAS refresh. Table 4.27 Refresh RAS Pulse Width RRA1 RRA0 Pulse width 1 1 0 0 1 0 1 0 5 cycles 4 cycles 3 cycles 2 cycles The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. The RRA can be read to obtain their set value. At cold start, RRA is set to "0" (2 cycles).
II CORE BLOCK: BCU (Bus Control Unit) A-1 SWAITE: #WAIT enable (D0) / Bus control register (0x4812E) Enable or disable wait cycle control via the #WAIT pin. Write "1": Enabled Write "0": Disabled Read: Valid A wait request from an SRAM device is made acceptable by writing "1" to SWAITE. The wait request signal input from the #WAIT pin is sampled at each falling edge of the bus clock when executing an SRAM read/write cycle.
II CORE BLOCK: BCU (Bus Control Unit) CRAS: Successive RAS mode (D8) / DRAM timing set-up register (0x48130) Set the successive RAS mode. Write "1": Successive RAS mode Write "0": Normal mode Read: Valid In systems using DRAM, the successive RAS mode is entered by writing "1" to CRAS. In this mode, read/write operations can be performed in page mode even when DRAM accesses do not occur back-to-back.
II CORE BLOCK: BCU (Bus Control Unit) A-1 A18IO: Areas 18–17 internal/external access selection (DF) / Access control register (0x48132) A16IO: Areas 16–15 internal/external access selection (DE) / Access control register (0x48132) A14IO: Areas 14–13 internal/external access selection (DD) / Access control register (0x48132) A12IO: Areas 12–11 internal/external access selection (DC) / Access control register (0x48132) A8IO: Areas 8–7 internal/external access selection (DA) / Access control register (0x4813
II CORE BLOCK: BCU (Bus Control Unit) A18RD: Areas 18–17 read signal (D7) / G/A read signal control register (0x48138) A16RD: Areas 16–15 read signal (D6) / G/A read signal control register (0x48138) A14RD: Areas 14–13 read signal (D5) / G/A read signal control register (0x48138) A12RD: Areas 12–11 read signal (D4) / G/A read signal control register (0x48138) A8RD: Areas 8–7 read signal (D2) / G/A read signal control register (0x48138) A6RD: Area 6 read signal (D1) / G/A read signal control register (0x481
II CORE BLOCK: BCU (Bus Control Unit) A-1 SDRENA: Enable SDRAM signals (D7) / SDRAM control register (0x39FFC1) Enable the pins used for the SDRAM. Write "1": Enabled Write "0": Disabled Read: Valid Writing "1" to SDRENA sets the pins shared with other functions to be used for the SDRAM, with the SDRAM clock output from the BCLK pin. If SDRENA = "0", the shared pins serve other functions. The SDRAM clock output from the BCLK pin is stopped in the HALT2 and the SLEEP modes.
II CORE BLOCK: BCU (Bus Control Unit) THIS PAGE IS BLANK.
II CORE BLOCK: ITC (Interrupt Controller) A-1 II-5 ITC (Interrupt Controller) The C33 Core Block contains an interrupt controller, making it possible to control all interrupts generated by the internal peripheral circuits. This section explains the functions of this interrupt controller centering around the method for controlling maskable interrupts.
II CORE BLOCK: ITC (Interrupt Controller) Contents of table "Hex No." indicates an interrupt number in hexadecimal value. "Vector number (Address)" indicates the trap table's vector number. The numerals in parentheses show an offset (in bytes) from the starting address (Base) of the trap table. The starting address (Base) of the trap table by default is the boot address, 0xC00000 set at an initial reset. This address can be changed using the TTBR register (0x48134 to 0x48137).
II CORE BLOCK: ITC (Interrupt Controller) A-1 Interrupt Factors and Intelligent DMA Several interrupt factors can be set so that they can invoke IDMA startup. When one of these interrupt factors occurs, IDMA is started up before an interrupt request to the CPU. The interrupt request to the CPU is generated after IDMA is completed. (The interrupt request can be disabled by a program.) IDMA is always started up regardless of how the PSR is set. For details, refer to "IDMA Invocation".
II CORE BLOCK: ITC (Interrupt Controller) Trap Table The C33 Core Block allows the base (starting) address of the trap table to be set by the TTBR register.
II CORE BLOCK: ITC (Interrupt Controller) A-1 Control of Maskable Interrupts Structure of the Interrupt Controller The interrupt controller is configured as shown in Figure 5.1.
II CORE BLOCK: ITC (Interrupt Controller) The IL is rewritten for only maskable interrupts and not for any other traps (except a reset). The IL is set to level 0 (that is, all interrupts above level 1 are enabled) by an initial reset. Note: As the S1C33000 Core CPU function, the IL allows interrupt levels to be set in the range of 0 to 15. However, since the interrupt priority register in the ITC consists of three bits, interrupt levels in each interrupt system can only be set for up to 8.
II CORE BLOCK: ITC (Interrupt Controller) A-1 Interrupt enable register This register controls the output of an interrupt request to the CPU. Only when the interrupt enable bit of this register is set to "1" can an interrupt request to the CPU be enabled by an occurrence of the corresponding interrupt factor. If the bit is set to "0", no interrupt request is made to the CPU even when the corresponding interrupt factor occurs. Interrupt enable bits can be read and written as for other registers.
II CORE BLOCK: ITC (Interrupt Controller) Interrupt Priority Register and Interrupt Levels The interrupt priority register is a 3-bit register provided for each interrupt system. It allows the interrupt levels of a given interrupt system to be set in the range of 0 to 7. The default priorities shown in Table 5.1 can be modified according to system requirements by this setting. The value set in this register is used by the interrupt controller and the CPU as described below.
II CORE BLOCK: ITC (Interrupt Controller) A-1 IDMA Invocation The interrupt factors for which IDMA channel numbers are written in Table 5.1 have the function to invoke the intelligent DMA (IDMA). IDMA request register The IDMA request register is used to specify the interrupt factor that invoke an IDMA transfer. If an IDMA request bit is set to "1", the IDMA request will be generated when the corresponding interrupt factor occurs.
II CORE BLOCK: ITC (Interrupt Controller) Interrupt after IDMA transfer To generate an interrupt after completion of IDMA transfer: The interrupt request that has been kept pending can be generated after completion of the DMA transfer. In this case, the interrupt must be enabled by the IDMA control information (DINTEM = "1") in adition to the interrupt controller and the PSR register settings.
II CORE BLOCK: ITC (Interrupt Controller) A-1 HSDMA Invocation Some interrupt factors can invoke high-speed DMAs (HSDMA). HSDMA trigger set-up register The DMA block contains four channel of HSDMA circuit. Each channel allows selection of an interrupt factor as the trigger. The HSDMA trigger set-up registers are used for this selection. HSDMA Ch.0: HSD0S[3:0] (D[3:0])/HSDMA Ch.0/1 trigger set-up register (0x40298) HSDMA Ch.1: HSD1S[3:0] (D[7:4])/HSDMA Ch.0/1 trigger set-up register (0x40298) HSDMA Ch.
II CORE BLOCK: ITC (Interrupt Controller) I/O Memory of Interrupt Controller Table 5.3 shows the control bits of the interrupt controller. Table 5.
II CORE BLOCK: ITC (Interrupt Controller) A-1 Register name Address Bit 16-bit timer 4/5 0040268 interrupt (B) priority register D7 D6 D5 D4 D3 D2 D1 D0 – P16T52 P16T51 P16T50 – P16T42 P16T41 P16T40 reserved 16-bit timer 5 interrupt level – 0 to 7 reserved 16-bit timer 4 interrupt level – 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 – PSI002 PSI001 PSI000 – P8TM2 P8TM1 P8TM0 reserved Serial interface Ch.
II CORE BLOCK: ITC (Interrupt Controller) Register name Address Bit 16-bit timer 4/5 0040274 interrupt (B) enable register D7 D6 D5–4 D3 D2 D1–0 E16TC5 E16TU5 – E16TC4 E16TU4 – Name 16-bit timer 5 comparison A 16-bit timer 5 comparison B reserved 16-bit timer 4 comparison A 16-bit timer 4 comparison B reserved Function 8-bit timer 0040275 interrupt (B) enable register D7–4 D3 D2 D1 D0 – E8TU3 E8TU2 E8TU1 E8TU0 reserved 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit
II CORE BLOCK: ITC (Interrupt Controller) A-1 Register name Address Bit Port input 4–7, 0040287 clock timer, A/D (B) interrupt factor flag register D7–6 D5 D4 D3 D2 D1 D0 Port input 0–3, high-speed DMA Ch. 0/1, 16-bit timer 0 IDMA request register Name Function – FP7 FP6 FP5 FP4 FCTM FADE reserved Port input 7 Port input 6 Port input 5 Port input 4 Clock timer A/D converter Setting – 1 Factor is generated 0 No factor is generated Init. R/W Remarks – X X X X X X – 0 when being read.
II CORE BLOCK: ITC (Interrupt Controller) Register name Address Bit Name High-speed DMA Ch.0/1 trigger set-up register D7 D6 D5 D4 HSD1S3 HSD1S2 HSD1S1 HSD1S0 High-speed DMA Ch.1 trigger set-up D3 D2 D1 D0 HSD0S3 HSD0S2 HSD0S1 HSD0S0 High-speed DMA Ch.0 trigger set-up D7 D6 D5 D4 HSD3S3 HSD3S2 HSD3S1 HSD3S0 High-speed DMA Ch.3 trigger set-up D3 D2 D1 D0 HSD2S3 HSD2S2 HSD2S1 HSD2S0 High-speed DMA Ch.2 trigger set-up High-speed DMA Ch.
II CORE BLOCK: ITC (Interrupt Controller) A-1 Register name Address Bit Interrupt factor 00402C5 FP function switching register D7 D6 T8CH5S0 SIO3TS0 8-bit timer 5 underflow SIO Ch.3 transmit buffer empty D5 D4 T8CH4S0 SIO3RS0 8-bit timer 4 underflow SIO Ch.3 receive buffer full D3 SIO2TS0 SIO Ch.2 transmit buffer empty D2 SIO3ES0 SIO Ch.3 receive error D1 SIO2RS0 SIO Ch.2 receive buffer full D0 SIO2ES0 SIO Ch.
II CORE BLOCK: ITC (Interrupt Controller) Register name Address Bit Areas 10–9 0048126 set-up register (HW) DF DE DD DC – A10IR2 A10IR1 A10IR0 Name reserved Area 10 internal ROM size selection Function DB DA D9 – A10BW1 A10BW0 reserved Areas 10–9 burst ROM burst read cycle wait control D8 D7 D6 D5 D4 A10DRA A9DRA A10SZ A10DF1 A10DF0 Area 10 burst ROM selection Area 9 burst ROM selection Areas 10–9 device size selection Areas 10–9 output disable delay time D3 D2 D1 D0 – A10WT2 A10WT1 A10WT0
II CORE BLOCK: ITC (Interrupt Controller) A-1 Fxxx: Interrupt factor flag Indicate the status of interrupt factors generated.
II CORE BLOCK: ITC (Interrupt Controller) DExxx: IDMA enable register Enable or disable the IDMA request. When using the set-only method (default) Write "1": IDMA enabled Write "0": Not changed Read: Valid When using the read/write method Write "1": IDMA enabled Write "0": IDMA disabled Read: Valid If a bit of this register is set to "1", the IDMA request by the interrupt factor is enabled. If the register bit is set to "0", the IDMA request is disabled.
II CORE BLOCK: ITC (Interrupt Controller) A-1 DENONLY: IDMA enable register set method selection (D2) / Flag set/reset method select register (0x4029F) Select the method for setting the IDMA enable registers. Write "1": Set-only method Write "0": Read/write method Read: Valid With the set-only method, IDMA enable bits are set by writing "1". The IDMA enable bits for which "0" has been written can neither be set nor reset. Therefore, this method ensures that only a specific IDMA enable bit is set.
II CORE BLOCK: ITC (Interrupt Controller) SIO2TS0: SIO Ch.2 transmit-buffer empty/FP3 interrupt factor switching (D3) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": SIO Ch.2 transmit-buffer empty Write "0": FP3 input Read: Valid Set to "1" to use the SIO Ch.2 transmit-buffer empty interrupt. Set to "0" to use the FP3 input interrupt. At power-on, this bit is set to "0". SIO3RS0: SIO Ch.
II CORE BLOCK: ITC (Interrupt Controller) A-1 SIO2RS1: SIO Ch.2 receive-buffer full/TM16 Ch.5 compare B interrupt factor switching (D0) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. Write "1": SIO Ch.2 receive-buffer full Write "0": TM16 Ch.5 compare B Read: Valid Set to "1" to use the SIO Ch.2 receive-buffer full interrupt. Set to "0" to use the TM16 Ch.5 compare B interrupt. At power-on, this bit is set to "0". SIO2TS1: SIO Ch.
II CORE BLOCK: ITC (Interrupt Controller) SIO3ES1: SIO Ch.3 receive error/TM16 Ch.3 compare A interrupt factor switching (D5) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. Write "1": SIO Ch.3 receive error Write "0": TM16 Ch.3 compare A Read: Valid Set to "1" to use the SIO Ch.3 receive error interrupt. Set to "0" to use the TM16 Ch.3 compare A interrupt. At power-on, this bit is set to "0". T8CH4S1: 8-bit timer 4 underflow/TM16 Ch.
II CORE BLOCK: ITC (Interrupt Controller) A-1 TTBR09–TTBR00: Trap table base address [9:0] (D[9:0]) / TTBR low-order register (0x48134[HW]) TTBR15–TTBR10: Trap table base address [15:10] (D[F:A]) / TTBR low-order register (0x48134[HW]) TTBR2B–TTBR20: Trap table base address [27:16] (D[B:0]) / TTBR high-order register (0x48136[HW]) TTBR33–TTBR30: Trap table base address [31:28] (D[F:C]) / TTBR high-order register (0x48136[HW]) Set the starting address of the trap table.
II CORE BLOCK: ITC (Interrupt Controller) THIS PAGE IS BLANK.
II CORE BLOCK: CLG (Clock Generator) A-1 II-6 CLG (Clock Generator) This section describes the method for controlling the system clock. Configuration of Clock Generator The C33 Core Block has a built-in clock generator that consists of a high-speed oscillation circuit (OSC3) and a PLL. The high-speed (OSC3) oscillation circuit generates the main clock for the CPU and internal peripheral circuits (e.g., DMA, serial interface, programmable timer, and A/D converter).
II CORE BLOCK: CLG (Clock Generator) I/O Pins of Clock Generator Table 6.1 lists the I/O pins of the clock generator. Table 6.
II CORE BLOCK: CLG (Clock Generator) A-1 PLL The PLL inputs the OSC3 clock and multiply its frequency. The multiply mode should be set using the PLLS[1:0] pins according to the OSC3 clock frequency. Table 6.2 Setting the PLLS[1:0] Pins PLLS1 PLLS0 Mode fin (OSC3 clock) fout Notes 1 0 0 1 1 0 x2 x4 PLL Not used 10 to 25 MHz 10 to 12.5 MHz – 20 to 50 MHz 40 to 50 MHz Not used No ROM, and 3.3 V ± 0.3 V No ROM, and 3.3 V ± 0.3 V Figure 6.
II CORE BLOCK: CLG (Clock Generator) Setting and Switching Over the CPU Operating Clock Setting the CPU operating clock frequency When operating the CPU with the high-speed (OSC3) clock, the operating frequency can be switched over in four steps. Use CLKDT[1:0] (D[7:6]) / Power control register (0x40180) for this switchover. Table 6.
II CORE BLOCK: CLG (Clock Generator) A-1 Power-Control Register Protection Flag The power-control register at address 0x40180, which is used to control the oscillation circuits and the CPU operating clock, is normally disabled against writing in order to prevent it from malfunctioning due to unnecessary writing. To enable this register for writing, the power-control register protection flag CLGP[7:0] (D[7:0]) / Power-control protection register (0x4019E) must be set to "0b10010110".
II CORE BLOCK: CLG (Clock Generator) I/O Memory of Clock Generator Table 6.4 lists the control bits of clock generator. Table 6.
II CORE BLOCK: CLG (Clock Generator) A-1 CLKCHG: CPU operating clock switch (D2) / Power control register (0x40180) Selects the CPU operating clock. Write "1": OSC3 clock Write "0": OSC1 clock Read: Valid The OSC3 clock is selected as the CPU operating clock by writing "1" to CLKCHG, and OSC1 is selected by writing "0". The operating clock can be switched over in this way only when both the high-speed (OSC3) and lowspeed (OSC1) oscillation circuits are on.
II CORE BLOCK: CLG (Clock Generator) Table 6.6 Operating Status in Standby Mode Standby mode HALT mode Basic mode Operating status • • • • • • HALT2 mode • • • • • • SLEEP mode • • • • • The CPU clock is stopped. (CPU stop status) BCU clock is supplied. (BCU run status) DMA clock is not stopped. (DMA run status) Clocks for the peripheral circuits maintain the status before entering HALT mode. (run or stop) The high-speed oscillation circuit maintains the status before entering HALT mode.
II CORE BLOCK: CLG (Clock Generator) A-1 Programming Notes (1) Immediately after the high-speed (OSC3) oscillation circuit is turned on, a certain period of time is required for oscillation to stabilize (for a 3.3-V crystal resonator, this time is 10 ms max.). To prevent the device from operating erratically, do not use the clock until its oscillation has stabilized.
II CORE BLOCK: CLG (Clock Generator) (8) If the IC enters the debug mode through the connected S5U1C33000H (In-Circuit Debugger for S1C33 Family) when the OSC3 clock is divided by 2, 4, or 8 using the CLKDT[1:0] (D[7:6])/Power control register (0x40180) to generate the CPU clock (CPU_CLK), the division ratio is automatically changed to 1/1. This may cause the CPU_CLK frequency to exceed the range assumed. Also it affects the BCU_CLK and BCLK output clocks as they are generated from CPU_CLK.
II CORE BLOCK: DBG (Debug Unit) A-1 II-7 DBG (Debug Unit) Debug Circuit The C33 Core Block has a built-in debug circuit. This functional block is provided to simply realize an advanced software development environment. Note: The debug circuit does not work during normal operation. To construct a software development environment using the debug circuit, the S5U1C33000H (In-Circuit Debugger for S1C33 Family) is separately required.
II CORE BLOCK: DBG (Debug Unit) THIS PAGE IS BLANK.
S1C33L03 FUNCTION PART III PERIPHERAL BLOCK
III PERIPHERAL BLOCK: INTRODUCTION A-1 III-1 INTRODUCTION The C33 peripheral block consists of a prescaler, six 8-bit programmable timer channels, six 16-bit programmable timer channels including watchdog timer and event counter functions, four serial interface channels, input and I/O ports, a low-speed (OSC1) oscillation circuit, and a clock timer.
III PERIPHERAL BLOCK: INTRODUCTION THIS PAGE IS BLANK.
III PERIPHERAL BLOCK: PRESCALER A-1 III-2 PRESCALER Configuration of Prescaler The prescaler divides the source clock (OSC3/PLL output clock or OSC1 clock) to generate the clocks for the internal peripheral circuits. The prescaler division ratio can be selected for each peripheral circuit in a program. A clock control circuit to control the clock supply to each peripheral circuit is also included.
III PERIPHERAL BLOCK: PRESCALER Selecting Division Ratio and Output Control for Prescaler The prescaler has registers for selecting the division ratio and clock output control separately for each peripheral circuit described above, allowing each peripheral circuit to be controlled. The prescaler's division ratio can be selected from among eight ratios set for each peripheral circuit through the use of the division ratio selection bits.
III PERIPHERAL BLOCK: PRESCALER A-1 I/O Memory of Prescaler Table 2.3 shows the control bits of the prescaler. Table 2.
III PERIPHERAL BLOCK: PRESCALER Register name Address Bit Name Function 16-bit timer 3 clock control register 004014A D7–4 – (B) D3 P16TON3 D2 P16TS32 D1 P16TS31 D0 P16TS30 reserved 16-bit timer 3 clock control 16-bit timer 3 clock division ratio selection 16-bit timer 4 clock control register 004014B D7–4 – (B) D3 P16TON4 D2 P16TS42 D1 P16TS41 D0 P16TS40 reserved 16-bit timer 4 clock control 16-bit timer 4 clock division ratio selection 16-bit timer 5 clock control register 004014C D7–4 – (B) D
III PERIPHERAL BLOCK: PRESCALER A-1 Register name Address Bit Name 8-bit timer 2/3 clock control register D7 D6 D5 D4 P8TON3 P8TS32 P8TS31 P8TS30 004014E (B) D3 D2 D1 D0 A/D clock 004014F control register (B) Power control register 0040180 (B) Prescaler clock 0040181 select register (B) Power control 004019E protect register (B) P8TON2 P8TS22 P8TS21 P8TS20 Function 8-bit timer 3 clock control 8-bit timer 3 clock division ratio selection 8-bit timer 2 clock control 8-bit timer 2 clock division
III PERIPHERAL BLOCK: PRESCALER CLGP7–CLGP0: Power-control register protection flag ([D[7:0]) / Power control protection register (0x4019E) These bits remove the protection against writing to addresses 0x40180 and 0x40190. Write "0b10010110": Write protection removed Write other than the above: No operation (write-protected) Read: Valid Before writing to address 0x40180 or 0x40190, set CLGP[7:0] to "0b10010110" to remove the protection against writing to that address.
III PERIPHERAL BLOCK: PRESCALER A-1 P16TON0: 16-bit timer 0 clock control (D3) / 16-bit timer 0 clock control register (0x40147) P16TON1: 16-bit timer 1 clock control (D3) / 16-bit timer 1 clock control register (0x40148) P16TON2: 16-bit timer 2 clock control (D3) / 16-bit timer 2 clock control register (0x40149) P16TON3: 16-bit timer 3 clock control (D3) / 16-bit timer 3 clock control register (0x4014A) P16TON4: 16-bit timer 4 clock control (D3) / 16-bit timer 4 clock control register (0x4014B) P16TON5: 1
III PERIPHERAL BLOCK: PRESCALER Programming Notes (1) For the prescaler clock, the clock source same as the CPU operating clock must be selected.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS A-1 III-3 8-BIT PROGRAMMABLE TIMERS Configuration of 8-Bit Programmable Timer The Peripheral Block contains six channels of 8-bit programmable timers (timers 0 to 5). Figure 3.1 shows the structure of the 8-bit programmable timer.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS Uses of 8-Bit Programmable Timers The down-counter of the 8-bit programmable timer cyclically outputs an underflow signal according to the preset data that is set in the software. This underflow signal is used to generate an interrupt request to the CPU or to control the internal peripheral circuits. In addition, this signal can be output to external devices.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS 8-bit programmable timer 2 • Clock supply to the Ch.0 serial interface When using the Ch.0 serial interface in the clock-synchronized master mode or the internal clock-based asynchronous mode, the output clock derived from the underflow signal of the 8-bit programmable timer 2 by dividing it by 2 is supplied to the serial interface as its operating clock. This enables the transfer rate of the serial interface to be programmed.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS Control and Operation of 8-Bit Programmable Timer With the 8-bit programmable timer, the following settings must first be made before it starts counting: 1. Setting the output pin (only when necessary) 2. Setting the input clock 3. Setting the preset data (initial counter value) 4. Setting the interrupt/IDMA/HSDMA Setting of an output pin is necessary only when the output clock of the 8-bit programmable timer is supplied to external devices.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS A-1 Setting preset data (initial counter value) Each timer has an 8-bit down-counter and a reload data register. The reload data register RLDx is used to set the initial value of the down-counter of each timer.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS When both the timer RUN/STOP control bit (PTRUNx) and the timer preset bit (PSETx) are set to "1" at the same time, the timer starts counting after presetting the reload register value into the counter. PTRUNx PSETx RLDx 0x10 0xA6 0xF3 Input clock PTDx7 PTDx6 PTDx5 PTDx4 PTDx3 PTDx2 PTDx1 PTDx0 Timer initial setup Preset Reload and interrupt Figure 3.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS A-1 Control of Clock Output When outputting an underflow signal of the 8-bit programmable timer to external devices, or when supplying a clock generated by the underflow signal to the serial interface, it is necessary to control the clock output of the timer.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS 8-Bit Programmable Timer Interrupts and DMA The 8-bit programmable timer has a function to generate an interrupt based on the underflow state of the timer 0 to 3. The timing at which an interrupt is generated is shown in Figure 3.2 in the preceding section. Control registers of the interrupt controller Table 3.3 shows the interrupt controller's control register provided for each timer. Table 3.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS A-1 High-speed DMA The underflow interrupt factor of the timer 0 to 3 can also invoke high-speed DMA (HSDMA). The following shows the HSDMA channel number and trigger set-up bit corresponding to the timer 0 to 3: Table 3.5 HSDMA Trigger Set-up Bits Timer HSDMA channel Timer 0 Timer 1 Timer 2 Timer 3 0 1 2 3 Trigger set-up bits HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298) HSD1S[3:0] (D[7:4]) / HSDMA Ch.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS I/O Memory of 8-Bit Programmable Timers Table 3.6 shows the control bits of the 8-bit programmable timers. For details on the I/O memory of the prescaler used to set a clock, refer to "Prescaler". Table 3.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS A-1 Register name Address Bit Name Function 8-bit timer 3 004016C D7–3 – control register (B) D2 PTOUT3 D1 PSET3 D0 PTRUN3 reserved 8-bit timer 3 clock output control 8-bit timer 3 preset 8-bit timer 3 Run/Stop control 8-bit timer 3 reload data register 004016D (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD37 RLD36 RLD35 RLD34 RLD33 RLD32 RLD31 RLD30 8-bit timer 3 reload data RLD37 = MSB RLD30 = LSB 8-bit timer 3 counter data register 004016E (B) D7 D6 D5 D4 D3
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS Register name Address Bit 8-bit timer 0040275 interrupt (B) enable register D7–4 D3 D2 D1 D0 – E8TU3 E8TU2 E8TU1 E8TU0 Name reserved 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow Function Setting 8-bit timer 0040285 interrupt factor (B) flag register D7–4 D3 D2 D1 D0 – F8TU3 F8TU2 F8TU1 F8TU0 reserved 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow –
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS A-1 CFP13–CFP10: P1[3:0] pin function selection (D[3:0]) / P1 function select register (0x402D4) Selects the pin that is used to output a timer underflow signal to external devices. Write "1": Underflow signal output pin Write "0": I/O port pin Read: Valid Select the pin used to output a timer underflow signal to external devices from among P10 through P13 by writing "1" to the corresponding bit, CFP10 through CFP13.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS PTD07–PTD00: Timer 0 counter data (D[7:0]) / 8-bit timer 0 counter data (0x40162) PTD17–PTD10: Timer 1 counter data (D[7:0]) / 8-bit timer 1 counter data (0x40166) PTD27–PTD20: Timer 2 counter data (D[7:0]) / 8-bit timer 2 counter data (0x4016A) PTD37–PTD30: Timer 3 counter data (D[7:0]) / 8-bit timer 3 counter data (0x4016E) PTD47–PTD40: Timer 4 counter data (D[7:0]) / 8-bit timer 4 counter data (0x40176) PTD57–PTD50: Timer 5 counter data (D[7:0]) / 8-bit ti
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS A-1 PTOUT0: Timer 0 clock output control register (D2) / 8-bit timer 0 control register (0x40160) PTOUT1: Timer 1 clock output control register (D2) / 8-bit timer 1 control register (0x40164) PTOUT2: Timer 2 clock output control register (D2) / 8-bit timer 2 control register (0x40168) PTOUT3: Timer 3 clock output control register (D2) / 8-bit timer 3 control register (0x4016C) PTOUT4: Timer 4 clock output control register (D2) / 8-bit timer 4 control register
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS F8TUx is the interrupt factor flag corresponding to each timer. It is set to "1" when the counter underflows. At this time, if the following conditions are met, an interrupt to the CPU is generated: 1. The corresponding interrupt enable register bit is set to "1". 2. No other interrupt request of a higher priority has been generated. 3. The IE bit of the PSR is set to "1" (interrupts enabled). 4.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS A-1 DE8TU0: Timer 0 IDMA enable (D2) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register (0x40296) DE8TU1: Timer 1 IDMA enable (D3) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register (0x40296) DE8TU2: Timer 2 IDMA enable (D4) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register (0x40296) DE8TU3: Timer 3 IDMA enable (D5) / 16-bit timer 5, 8-bit timer, serial I/F Ch.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS THIS PAGE IS BLANK.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS A-1 III-4 16-BIT PROGRAMMABLE TIMERS Configuration of 16-Bit Programmable Timer The Peripheral Block contains six systems of 16-bit programmable timers (timers 0 to 5). They also have an event counter function using an I/O port pin. Note: On the following pages, each timer is identified as timer x (x = 0 to 5). The functions and control register structures of 16-bit programmable timers 0 to 5 are the same.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS I/O Pins of 16-Bit Programmable Timers Table 4.1 shows the input/output pins used for the 16-bit programmable timers. Table 4.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS A-1 Uses of 16-Bit Programmable Timers The up-counters of the 16-bit programmable timer cyclically output a comparison-match signal in accordance with the comparison data that are set in the software. This signal is used to generate an interrupt request to the CPU or control the internal peripheral circuits. A clock generated from the signal can also be output to external devices.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Control and Operation of 16-Bit Programmable Timer The following settings must first be made before the 16-bit programmable timer starts counting: 1. Setting pins for input/output (only when necessary) 2. Setting input clock 3. Selecting comparison data register/buffer 4. Setting clock output conditions (signal active level, fine mode) 5. Setting comparison data 6.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS • External clock When using the timer as an event counter by supplying clock pulses from an external source, make sure the event cycle is at least the CPU operating clock period. A-1 Selecting comparison data register/buffer The comparison data registers A and B are used to store the data to be compared with the content of the upcounter. This register can be directly read and written.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Resetting the counter Each timer includes the PRESETx bit to reset the counter.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS A-1 Controlling Clock Output The timers can generate a TMx signal using the comparison match signals from the counter. Setting the signal active level By default, an active high signal (normal low) is generated. This logic can be inverted using the OUTINVx bit. When "1" is written to the OUTINVx bit, the timer generates an active low (normal high) signal.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS When OUTINVx = "0" (active high): The timer outputs a low level until the counter becomes equal to the comparison data A set in the CRxA register. When the counter is incremented to the next value from the comparison data A, the output pin goes high and a comparison A interrupt occurs. When the counter becomes equal to the comparison data B set in the CRxB register, the counter is reset and the output pin goes low.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS A-1 16-Bit Programmable Timer Interrupts and DMA The 16-bit programmable timer has a function for generating an interrupt using the comparison match A and B states. The timing at which an interrupt is generated is shown in Figure 4.2 in the preceding section. Control registers of the interrupt controller Table 4.4 shows the control registers of the interrupt controller provided for each timer. Table 4.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS For IDMA to be invoked, the IDMA request and IDMA enable bits shown in Table 4.5 must be set to "1" in advance. Transfer conditions, etc. must also be set on the IDMA side in advance. Table 4.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS A-1 Trap vectors The trap vector addresses for each default interrupt factor are set as shown below: Timer 0 comparison B: Timer 0 comparison A: Timer 1 comparison B: Timer 1 comparison A: Timer 2 comparison B: Timer 2 comparison A: Timer 3 comparison B: Timer 3 comparison A: Timer 4 comparison B: Timer 4 comparison A: Timer 5 comparison B: Timer 5 comparison A: 0x0C00078 0x0C0007C 0x0C00088 0x0C0008C 0x0C00098 0x0C0009C 0x0C000A8 0x0C000AC 0x0C000B8 0x0C0
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS I/O Memory of 16-Bit Programmable Timers Table 4.7 shows the control bits of the 16-bit programmable timers. For details on the I/O memory of the prescaler used to set a clock, refer to "Prescaler". Table 4.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS A-1 Register name Address Bit Name Port input 0–3, high-speed DMA Ch. 0/1, 16-bit timer 0 IDMA request register 0040290 (B) D7 D6 D5 D4 D3 D2 D1 D0 R16TC0 R16TU0 RHDM1 RHDM0 RP3 RP2 RP1 RP0 16-bit timer 0 comparison A 16-bit timer 0 comparison B High-speed DMA Ch.1 High-speed DMA Ch.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Register name Address Bit P2 function select register 00402D8 (B) D7 D6 D5 D4 D3 D2 D1 D0 CFP27 CFP26 CFP25 CFP24 CFP23 CFP22 CFP21 CFP20 Name P27 function selection P26 function selection P25 function selection P24 function selection P23 function selection P22 function selection P21 function selection P20 function selection Function 1 1 1 1 1 1 1 1 Setting Port function extension register 00402DF (B) D7 D6 D5 D4 D3 D2 D1 CFEX7 CFEX6 CFEX5 CFEX4
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS A-1 Register name Address Bit Name Function Setting 16-bit timer 1 comparison data A set-up register 0048188 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 1 comparison data B set-up register 004818A (HW) 16-bit timer 1 counter data register 004818C (HW) CR1A15 CR1A14 CR1A13 CR1A12 CR1A11 CR1A10 CR1A9 CR1A8 CR1A7 CR1A6 CR1A5 CR1A4 CR1A3 CR1A2 CR1A1 CR1A0 16-bit timer 1 comparison data A CR1A15 = MSB CR1A0 = LSB 0 to 65535 X
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Register name Address Bit Name Function Setting 16-bit timer 2 comparison data B set-up register 0048192 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR2B15 CR2B14 CR2B13 CR2B12 CR2B11 CR2B10 CR2B9 CR2B8 CR2B7 CR2B6 CR2B5 CR2B4 CR2B3 CR2B2 CR2B1 CR2B0 16-bit timer 2 comparison data B CR2B15 = MSB CR2B0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 2 counter data register 0048194 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS A-1 Register name Address Bit 16-bit timer 3 counter data register 004819C (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC315 TC314 TC313 TC312 TC311 TC310 TC39 TC38 TC37 TC36 TC35 TC34 TC33 TC32 TC31 TC30 16-bit timer 3 counter data TC315 = MSB TC30 = LSB 16-bit timer 3 004819E control register (B) D7 D6 D5 D4 D3 D2 D1 D0 – SELFM3 SELCRB3 OUTINV3 CKSL3 PTM3 PRESET3 PRUN3 reserved 16-bit timer 3 fine mode selection 16-bit timer 3 comparison
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Register name Address Bit Name Function Setting 16-bit timer 4 00481A6 control register (B) D7 D6 D5 D4 D3 D2 D1 D0 – SELFM4 SELCRB4 OUTINV4 CKSL4 PTM4 PRESET4 PRUN4 reserved 16-bit timer 4 fine mode selection 16-bit timer 4 comparison buffer 16-bit timer 4 output inversion 16-bit timer 4 input clock selection 16-bit timer 4 clock output control 16-bit timer 4 reset 16-bit timer 4 Run/Stop control – 16-bit timer 5 comparison data A set-up register
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS A-1 CFP16–CFP10: P1[6:0] pin function selection (D[6:0]) / P1 function select register (0x402D4) Selects the pin to be used for input of an external count clock to the timer. Write "1": Clock input pin Write "0": I/O port pin Read: Valid Select clock input pins for the timers that are used as an event counter from among P10 through P16, by writing "1" to CFP10–CFP16. For the relationship between each pin and timer, refer to Table 4.1.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS SELFM0: Timer 0 fine mode selection (D6) / 16-bit timer 0 control register (0x48186) SELFM1: Timer 1 fine mode selection (D6) / 16-bit timer 1 control register (0x4818E) SELFM2: Timer 2 fine mode selection (D6) / 16-bit timer 2 control register (0x48196) SELFM3: Timer 3 fine mode selection (D6) / 16-bit timer 3 control register (0x4819E) SELFM4: Timer 4 fine mode selection (D6) / 16-bit timer 4 control register (0x481A6) SELFM5: Timer 5 fine mode selection (
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS A-1 CKSL0: Timer 0 input clock selection (D3) / 16-bit timer 0 control register (0x48186) CKSL1: Timer 1 input clock selection (D3) / 16-bit timer 1 control register (0x4818E) CKSL2: Timer 2 input clock selection (D3) / 16-bit timer 2 control register (0x48196) CKSL3: Timer 3 input clock selection (D3) / 16-bit timer 3 control register (0x4819E) CKSL4: Timer 4 input clock selection (D3) / 16-bit timer 4 control register (0x481A6) CKSL5: Timer 5 input clock s
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS PRUN0: Timer 0 RUN/STOP control (D0) / 16-bit timer 0 control register (0x48186) PRUN1: Timer 1 RUN/STOP control (D0) / 16-bit timer 1 control register (0x4818E) PRUN2: Timer 2 RUN/STOP control (D0) / 16-bit timer 2 control register (0x48196) PRUN3: Timer 3 RUN/STOP control (D0) / 16-bit timer 3 control register (0x4819E) PRUN4: Timer 4 RUN/STOP control (D0) / 16-bit timer 4 control register (0x481A6) PRUN5: Timer 5 RUN/STOP control (D0) / 16-bit timer 5 con
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS A-1 TC015–TC00: Timer 0 counter data (D[F:0]) / 16-bit timer 0 counter data register (0x48184) TC115–TC10: Timer 1 counter data (D[F:0]) / 16-bit timer 1 counter data register (0x4818C) TC215–TC20: Timer 2 counter data (D[F:0]) / 16-bit timer 2 counter data register (0x48194) TC315–TC30: Timer 3 counter data (D[F:0]) / 16-bit timer 3 counter data register (0x4819C) TC415–TC40: Timer 4 counter data (D[F:0]) / 16-bit timer 4 counter data register (0x481A4) TC5
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS F16TUx and F16TCx are the interrupt factor flags corresponding to the comparison B and comparison A interrupts, respectively. The flag is set to "1" when each interrupt factor occurs. At this time, if the following conditions are met, an interrupt to the CPU is generated: 1. The corresponding interrupt enable register bit is set to "1". 2. No other interrupt request of a higher priority has been generated. 3.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS A-1 DE16TU0, DE16TC0: Timer 0 IDMA enable (D6, D7) / Port input 0–3, HSDMA, 16-bit timer 0 IDMA enable register (0x40294) DE16TU1, DE16TC1: Timer 1 IDMA enable (D0, D1) / 16-bit timer 1–4 IDMA enable register (0x40295) DE16TU2, DE16TC2: Timer 2 IDMA enable (D2, D3) / 16-bit timer 1–4 IDMA enable register (0x40295) DE16TU3, DE16TC3: Timer 3 IDMA enable (D4, D5) / 16-bit timer 1–4 IDMA enable register (0x40295) DE16TU4, DE16TC4: Timer 4 IDMA enable (D6, D7) /
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS THIS PAGE IS BLANK.
III PERIPHERAL BLOCK: WATCHDOG TIMER A-1 III-5 WATCHDOG TIMER Configuration of Watchdog Timer The Peripheral Block incorporates a watchdog timer function to detect the CPU's crash. This function is implemented through the use of the 16-bit programmable timer 0. When this function is enabled, an NMI (nonmaskable interrupt) is generated by the comparison B signal from the 16-bit programmable timer 0 (generating intervals can be set through the use of software).
III PERIPHERAL BLOCK: WATCHDOG TIMER Resetting the watchdog timer When using the watchdog timer, prepare a routine to reset the 16-bit programmable timer 0 before an NMI is generated in a location where it will be periodically processed. Make sure this routine is processed within the NMI generation interval described above. The 16-bit programmable timer 0 is reset by writing "1" to PRESET0 (D1) / 16-bit timer 0 control register (0x48186).
III PERIPHERAL BLOCK: WATCHDOG TIMER A-1 I/O Memory of Watchdog Timer Table 5.1 shows the control bits of the watchdog timer. Table 5.1 Control Bits of Watchdog Timer Register name Address Bit Name Function Setting Init. R/W Remarks Watchdog 0040170 timer write(B) protect register D7 WRWD D6–0 – EWD write protection – 1 Write enabled 0 Write-protect – 0 – R/W – 0 when being read.
III PERIPHERAL BLOCK: WATCHDOG TIMER THIS PAGE IS BLANK.
III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT A-1 III-6 LOW-SPEED (OSC1) OSCILLATION CIRCUIT Configuration of Low-Speed (OSC1) Oscillation Circuit The Peripheral Block has a built-in low-speed (OSC1) oscillation circuit. The low-speed (OSC1) oscillation circuit generates a 32.768-kHz (Typ.) subclock. The OSC1 clock output by this circuit is delivered to the CLG (clock generator) in the Core Block and is used as the source clock for the clock timer.
III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT Oscillator Types In the low-speed (OSC1) oscillation circuit, either a crystal oscillation or an external clock input can be selected as the type of oscillation circuit. Figure 6.2 shows the structure of the low-speed (OSC1) oscillation circuit. CG1 OSC1 VDD VSS fOSC1 Rf CD1 VSS X'tal1 OSC2 OSC1 fOSC1 External clock N.C.
III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT A-1 Controlling Oscillation The low-speed (OSC1) oscillation circuit can be turned on or off using SOSC1 (D0) / Power control register (0x40180). The oscillation circuit is turned off by writing "0" to SOSC1 and turned back on again by writing "1". SOSC1 is set to "1" at initial reset, so the oscillation circuit is turned on.
III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT Power-Control Register Protection Flag The power-control register (SOSC1, SOSC3, CLKCHG, CLKDT[1:0]) at address 0x40180, which is used to control the oscillation circuits and the CPU operating clock, is normally disabled against writing in order to prevent it from malfunctioning due to unnecessary writing.
III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT A-1 I/O Memory of Low-Speed (OSC1) Oscillation Circuit Table 6.3 lists the control bits of the low-speed (OSC1) oscillation circuit. Table 6.
III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT SOSC1: Low-speed (OSC1) oscillation control (D0) / Power control register (0x40180) Turns the low-speed (OSC1) oscillation on or off. Write "1": OSC1 oscillation turned on Write "0": OSC1 oscillation turned off Read: Valid The oscillation of the low-speed (OSC1) oscillation circuit is stopped by writing "0" to SOSC1, and started again by writing "1".
III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT A-1 The following shows the operating status in HALT mode (basic mode and HALT2 mode) and SLEEP mode. Table 6.4 Operating Status in Standby Mode Standby mode HALT mode Basic mode Operating status • • • • • • HALT2 mode • • • • • • SLEEP mode • • • • • The CPU clock is stopped. (CPU stop status) BCU clock is supplied. (BCU run status) DMA clock is not stopped.
III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT CFP14: P14 function selection (D4) / P1 function select register (0x402D4) Selects the pin function of the P14 I/O port. Write "1": OSC1 clock output pin Write "0": I/O port pin Read: Invalid The P14 pin is set for OSC1 clock output (FOSC1) by writing "1" to CFP14. When this pin is used as the FOSC1 output pin, also set IOC14 (D4/0x402D6 ) to "1" (output). At cold start, CFP14 is set to "0" (I/O port pin).
III PERIPHERAL BLOCK: CLOCK TIMER A-1 III-7 CLOCK TIMER Configuration of Clock Timer The clock timer consists of an 8-bit binary counter that is clocked by a 256-Hz signal derived from the low-speed (OSC1) oscillation clock fOSC1, and second, minute, hour, and day counters, allowing all data (128 Hz to 1 Hz, seconds, minutes, hours, and day) to be read out in a software.
III PERIPHERAL BLOCK: CLOCK TIMER Control and Operation of the Clock Timer Initial setting At initial reset, the clock timer's counter data, setup contents of alarms, and control bits including RUN/STOP, are not initialized. (This does not include the CPU core power on/off flag TCHVOF or OSC1 auto-off flag TCAOFF.) Therefore, when using the clock timer, initialize it as follows: 1. Before you start setting up, stop the clock timer and disable the clock timer interrupt. 2. Reset the counters. 3.
III PERIPHERAL BLOCK: CLOCK TIMER A-1 RUN/STOP the clock timer The clock timer starts counting when "1" is written to TCRUN (D0) / Clock timer Run/Stop register (0x40151) and stops counting when "0" is written. When the clock timer is made to RUN, the 256-Hz clock input is enabled at a falling edge of the low-speed (OSC1) oscillation clock pulse, and the 8-bit binary counter counts up at each falling edge of this 256-Hz clock. Figure 7.2 shows the operation of the 8-bit binary counter.
III PERIPHERAL BLOCK: CLOCK TIMER Setting alarm function The clock timer has an alarm function, enabling an interrupt to be generated at a specified time and day. This specification can be made in minutes, hours, and days for each alarm or a combination of multiple alarms. Use TCASE[2:0] (D[4:2) / Clock timer interrupt control register (0x40152) for this specification. Table 7.
III PERIPHERAL BLOCK: CLOCK TIMER A-1 An interrupt can be generated on a specified alarm day at a specified time as described in the preceding section. Interrupts generated by a signal and those generated by an alarm can both be used. However, since the clock timer has only one interrupt factor flag, it is the same interrupt that is generated by the timer.
III PERIPHERAL BLOCK: CLOCK TIMER Examples of Use of Clock Timer The following shows examples of use of the clock timer and how to control the timer in each case. To use the clock timer as a timer/counter Example in which while the CPU is inactive, the clock timer is kept operating in order to start again the CPU after a specified length of time has elapsed (e.g., three days): 1. Make sure the low-speed (OSC1) oscillation circuit is oscillating stably (SOSC1 = "1").
III PERIPHERAL BLOCK: CLOCK TIMER A-1 I/O Memory of Clock Timer Table 7.5 shows the control bits of the clock timer. Table 7.5 Control Bits of Clock Timer Register name Address Clock timer Run/Stop register 0040151 (B) Clock timer 0040152 interrupt (B) control register Bit Name D7–2 – D1 TCRST D0 TCRUN Function reserved Clock timer reset Clock timer Run/Stop control Setting Init. R/W – 1 Reset 1 Run Remarks – X X – 0 when being read. W 0 when being read.
III PERIPHERAL BLOCK: CLOCK TIMER Register name Address Clock timer minute comparison register 0040159 (B) Clock timer hour comparison register Clock timer day comparison register Bit D7–6 D5 D4 D3 D2 D1 D0 Name – TCCH5 TCCH4 TCCH3 TCCH2 TCCH1 TCCH0 Function reserved Clock timer minute comparison data TCCH5 = MSB TCCH0 = LSB Setting Init. R/W Remarks – 0 to 59 minutes (Note) Can be set within 0–63. – X X X X X X – 0 when being read.
III PERIPHERAL BLOCK: CLOCK TIMER A-1 TCRUN: Clock timer RUN/STOP control (D0) / Clock timer Run/Stop register (0x40151) Controls the RUN/STOP of the clock timer. Write "1": RUN Write "0": STOP Read: Valid The clock timer is made to start counting by writing "1" to the TCRUN register and made to stop by writing "0". The timer data is retained even in the STOP state. The timer can also be made to start counting from the retained data by changing its state from STOP to RUN.
III PERIPHERAL BLOCK: CLOCK TIMER TCASE2–TCASE0: Alarm factor select register (D[4:2]) / Clock timer interrupt control register (0x40152) Selects the factor for which an alarm is to be generated. Table 7.7 Selecting Alarm Factor TCASE2 TCASE1 TCASE0 X X 1 0 X 1 X 0 1 X X 0 Alarm factor Minute alarm Hour alarm Day alarm None Use the TCASE2, TCASE1, and TCASE0 bits to select a day, hour, and minute alarm, respectively. It is therefore possible to select multiple alarm factors.
III PERIPHERAL BLOCK: CLOCK TIMER A-1 ECTM: Clock timer interrupt enable (D1) / Port input 4–7, clock timer, A/D interrupt enable register (0x40277) Enables or disables generation of an interrupt to the CPU. Write "1": Interrupt enabled Write "0": Interrupt disabled Read: Valid This bit controls the clock timer interrupt. The interrupt is enabled by setting ECTM to "1" and is disabled by setting it to "0". At initial reset, ECTM is set to "0" (interrupt disabled).
III PERIPHERAL BLOCK: CLOCK TIMER Programming Notes (1) The low-speed (OSC1) oscillation circuit, which is the clock source for the clock timer, requires a muxmum of three seconds for its oscillation to stabilize after it is started up. Therefore, immediately after power-on, wait until the oscillation stabilizes before starting the clock timer. (2) At initial reset, the clock timer counter data, the setup contents of alarms, and control bits, including RUN/STOP, are not initialized.
III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 III-8 SERIAL INTERFACE Configuration of Serial Interfaces Features of Serial Interfaces The Peripheral Block contains four channels (Ch.0, Ch.1, Ch.2 and Ch.3) of serial interfaces, the features of which are described below. The functions of these four serial interfaces are the same. • A clock-synchronized or asynchronous mode can be selected for the transfer method.
III PERIPHERAL BLOCK: SERIAL INTERFACE I/O Pins of Serial Interface Table 8.1 lists the I/O pins used by the serial interface. Table 8.
III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 Setting Transfer Mode The transfer mode of the serial interface can be set using SMDx[1:0] individually for each channel as shown in Table 8.2 below. Table 8.2 Transfer Mode SMDx1 SMDx0 Transfer mode 1 1 0 0 1 0 1 0 8-bit asynchronous mode 7-bit asynchronous mode Clock-synchronized slave mode Clock-synchronized master mode At initial reset, SMDx becomes indeterminate, so be sure to initialize it in the software.
III PERIPHERAL BLOCK: SERIAL INTERFACE Clock-Synchronized Interface Outline of Clock-Synchronized Interface In the clock-synchronized transfer mode, 8 bits of data are synchronized to the common clock on both the transmit and receive sides when the data is transferred. Since the transmit and receive units both have a double-buffer structure, successive transmit and receive operations are possible. Since the clock line is shared between the transmit and receive units, the communication mode is half-duplex.
III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 Setting Clock-Synchronized Interface When performing clock-synchronized transfers via the serial interface, the following settings must be made before data transfer is actually begun: 1. Setting input/output pins 2. Setting the interface mode 3. Setting the transfer mode 4. Setting the input clock 5. Setting interrupts and IDMA/HSDMA The following explains the content of each setting.
III PERIPHERAL BLOCK: SERIAL INTERFACE RLD = fPSCIN × pdr - 1 2 × bps RLD: fPSCIN: bps: pdr: (Eq. 1) Reload data register setup value of the 8-bit programmable timer Prescaler input clock frequency (Hz) Transfer rate (bits/second) Division ratio of the prescaler Note: The division ratios selected by the prescaler differ between 8-bit programmable timers 2 and 3, so be careful when setting the ratio.
III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 Control and Operation of Clock-Synchronized Transfer Transmit control (1) Enabling transmit operation Use the transmit-enable bit TXENx for transmit control. Ch.0 transmit-enable: TXEN0 (D7) / Serial I/F Ch.0 control register (0x401E3) Ch.1 transmit-enable: TXEN1 (D7) / Serial I/F Ch.1 control register (0x401E8) Ch.2 transmit-enable: TXEN2 (D7) / Serial I/F Ch.2 control register (0x401F3) Ch.3 transmit-enable: TXEN3 (D7) / Serial I/F Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE • Clock-synchronized master mode The timing at which the device starts transmitting in the master mode is as follows: When #SRDY is on a low level while TDBEx = "0" (the transmit-data register contains data written to it) or when TDBEx is set to "0" (data has been written to the transmit-data register) while #SRDY is on a low level. Figure 8.4 shows a transmit timing chart in the clock-synchronized master mode.
III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 3. The data in the shift register is shifted 1 bit by the next falling edge of the clock, and the bit following the LSB is output from SOUTx. This operation is repeated until all 8 bits of data are transmitted. 4. The #SRDYx signal is set to a low level when the last bit (8th bit) is output from the SOUTx pin. The master device must take in each bit synchronously with the rising edges of the synchronizing clock.
III PERIPHERAL BLOCK: SERIAL INTERFACE A status bit is also provided that indicates the status of the receive data register. Ch.0 receive data buffer full: RDBF0 (D0) / Serial I/F Ch.0 status register (0x401E2) Ch.1 receive data buffer full: RDBF1 (D0) / Serial I/F Ch.1 status register (0x401E7) Ch.2 receive data buffer full: RDBF2 (D0) / Serial I/F Ch.2 status register (0x401F2) Ch.3 receive data buffer full: RDBF3 (D0) / Serial I/F Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 1. After setting the #SRDYx signal to a low level (ready to receive), the slave waits for clock input from the master. 2. The master device outputs each bit of data synchronously with the falling edges of the clock. The LSB is output first. 3. This serial interface takes the SIN input into the shift register at the rising edges of the clock that is input from #SCLKx. The data in the shift register is sequentially shifted as bits are taken in.
III PERIPHERAL BLOCK: SERIAL INTERFACE Asynchronous Interface Outline of Asynchronous Interface Asynchronous transfers are performed by adding a start bit and a stop bit to the start and end points of each serialconverted data. With this method, there is no need to use a clock that is fully synchronized on the transmit and receive sides; instead, transfer operations are timed by the start and stop bits added to the start and end points of each data.
III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 Setting Asynchronous Interface When performing asynchronous transfer via the serial interface, the following must be done before data transfer can be started: 1. Setting input/output pins 2. Setting the interface mode 3. Setting the transfer mode 4. Setting the input clock 5. Setting the data format 6. Setting interrupt/IDMA/HSDMA The following describes how to set each of the above.
III PERIPHERAL BLOCK: SERIAL INTERFACE Any desired clock frequency can be obtained by setting the prescaler division ratio and the reload data of the 8-bit programmable timer as necessary. The relationship between the contents of these setting and the transfer rate is expressed by Eq. 2. The 8-bit programmable timer has its underflow signal further divided by 2 internally, in order to ensure that the duty ratio of the clock supplied to the serial interface is 50%.
III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 • Sampling clock In the asynchronous mode, TCLK (the clock output by the 8-bit programmable timer or input from the #SCLKx pin) is internally divided in the serial interface, in order to create a sampling clock. A 1/16 division ratio is selected by writing "0" to DIVMDx , and a 1/8 ratio is selected by writing "1". Ch.0 clock division ratio selection: DIVMD0 (D4) / Serial I/F Ch.0 IrDA register (0x401E4) Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE Setting the data format In the asynchronous mode, the data length is 7 or 8 bits as determined by the transfer mode set. The start bit is fixed at 1. The stop and parity bits can be set as shown in the Table 8.5 using the following control bits: Ch.0 (Serial I/F Ch.0 control register) Stop-bit selection Parity enable Parity-mode selection STPB0(D3/0x401E3) EPR0(D5/0x401E3) PMD0(D4/0x401E3) Table 8.5 Serial I/F Control Bits Ch.1 (Serial I/F Ch.1 Ch.2 (Serial I/F Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 The transfer status can be checked using the transmit-completion flag (TENDx). Ch.0 transmit-completion flag: TEND0 (D5) / Serial I/F Ch.0 status register (0x401E2) Ch.1 transmit-completion flag: TEND1 (D5) / Serial I/F Ch.1 status register (0x401E7) Ch.2 transmit-completion flag: TEND2 (D5) / Serial I/F Ch.2 status register (0x401F2) Ch.3 transmit-completion flag: TEND3 (D5) / Serial I/F Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE Receive control (1) Enabling receive operations Use the receive-enable bit RXENx for receive control. Ch.0 receive-enable: RXEN0 (D6) / Serial I/F Ch.0 control register (0x401E3) Ch.1 receive-enable: RXEN1 (D6) / Serial I/F Ch.1 control register (0x401E8) Ch.2 receive-enable: RXEN2 (D6) / Serial I/F Ch.2 control register (0x401F3) Ch.3 receive-enable: RXEN3 (D6) / Serial I/F Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 Note: The receive operation is terminated when the first stop bit is sampled even if the stop bit is configured with two bits. • Successive receive operations When the data received in the shift register is transferred to the receive data register, RDBFx is set to "1" (buffer full), indicating that the received data can be read out. Thereafter, data can be received successively because the receive data register can be read out while the next data is received.
III PERIPHERAL BLOCK: SERIAL INTERFACE • Overrun error If during successive receive operations, a receive operation for the next data is completed before the receive data register is read out, the receive data register is overwritten with the new data. Therefore, the receive data register must always be read out before a receive operation for the next data is completed. When the receive data register is overwritten, an overrun error is generated and the overrun-error flag is set to "1". Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 IrDA Interface Outline of IrDA Interface Each channel of the serial interface contains a PPM modulator circuit, allowing an infrared-ray communication circuit to be configured based on IrDA 1.0 simply by adding a simple external circuit. Infrared communication module S1C33 LED A PPM Modulator SOUTx LED TXD VP1N LED C Serial I/F Photodiode PPM Modulator SINx RXD CX1 VDD Vcc CX2 VSS VP1N GND (Example: HP HSDL-1000) Figure 8.
III PERIPHERAL BLOCK: SERIAL INTERFACE Selecting the IrDA interface function To use the IrDA interface function, select it using the control bits shown below and then set the 8-bit (or 7bit) asynchronous mode as the transfer mode. Ch.0 IrDA interface-function selection: IRMD0[1:0] (D[1:0]) / Serial I/F Ch.0 IrDA register (0x401E4) Ch.1 IrDA interface-function selection: IRMD1[1:0] (D[1:0]) / Serial I/F Ch.1 IrDA register (0x401E9) Ch.2 IrDA interface-function selection: IRMD2[1:0] (D[1:0]) / Serial I/F Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 Control and Operation of IrDA Interface The transmit/receive procedures have been explained in the section on the asynchronous interface, so refer to "Control and Operation of Asynchronous Transfer". The following describes the data modulation and demodulation performed using the PPM modulator circuit: When transmitting During data transmission, the pulse width of the serial interface output signal is set to 3/16 before the signal is output from the SOUTx pin.
III PERIPHERAL BLOCK: SERIAL INTERFACE Serial Interface Interrupts and DMA The serial interface can generate the following three types of interrupts in each channel: • Transmit-buffer empty interrupt • Receive-buffer full interrupt • Receive-error interrupt Transmit-buffer empty interrupt factor This interrupt factor occurs when the transmit data set in the transmit data register is transferred to the shift register, in which case the interrupt factor flag FSTXx is set to "1".
III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 The interrupt priority register sets the interrupt priority level of each interrupt source in a range between 0 and 7. An interrupt request to the CPU is accepted only when no other interrupt request of a higher priority has been generated.
III PERIPHERAL BLOCK: SERIAL INTERFACE If an interrupt factor occurs when the IDMA request and enable bits are set to "1", IDMA is invoked. No interrupt request is generated at that point. An interrupt request is generated upon completion of the DMA transfer. The bits can also be set so as not to generate an interrupt, with only a DAM transfer performed. For details on DMA transfer and how to control interrupts upon completion of DMA transfer, refer to "IDMA (Intelligent DMA)". • Ch.2 and Ch.3 For Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE • Ch.2 and Ch.3 For Ch.2 and Ch.3, either port input interrupts or 16-bit timer interrupts are selected, and HSDMA is invoked by means of those interrupt factor (See Table 8.10). When port input interrupts are selected, Serial I/F Ch.2 receive buffer full corresponds to port 1, and transmit buffer empty to port 3. Therefore, HSDMA can be invoked by setting HSDMA Ch.1 and Ch.3 trigger factor values (D[7:4]/0x40298, D[7:4]/0x40299) of "0011".
III PERIPHERAL BLOCK: SERIAL INTERFACE I/O Memory of Serial Interface Table 8.14 shows the control bits of the serial interface. For details on the I/O memory of the prescaler that is used to set clocks, as well of that of 8-bit programmable timers, refer to "Prescaler" and "8-Bit Programmable Timers", respectively. Table 8.14 Control Bits of Serial Interface Register name Address Bit Name Serial I/F Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 Register name Address Bit Name Function Serial I/F Ch.1 00401E7 D7–6 – status register (B) D5 TEND1 D4 FER1 D3 PER1 D2 OER1 D1 TDBE1 D0 RDBF1 – Ch.1 transmit-completion flag Ch.1 flaming error flag Ch.1 parity error flag Ch.1 overrun error flag Ch.1 transmit data buffer empty Ch.1 receive data buffer full Serial I/F Ch.1 00401E8 control register (B) Ch.1 transmit enable Ch.1 receive enable Ch.1 parity enable Ch.1 parity mode selection Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE Register name Address Bit Serial I/F Ch.3 transmit data register 00401F5 (B) D7 D6 D5 D4 D3 D2 D1 D0 TXD37 TXD36 TXD35 TXD34 TXD33 TXD32 TXD31 TXD30 Serial I/F Ch.3 transmit data TXD37(36) = MSB TXD30 = LSB 0x0 to 0xFF(0x7F) X X X X X X X X R/W Serial I/F Ch.3 receive data register 00401F6 (B) D7 D6 D5 D4 D3 D2 D1 D0 RXD37 RXD36 RXD35 RXD34 RXD33 RXD32 RXD31 RXD30 Serial I/F Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 Register name Address Bit Name Function Serial I/F 0040286 interrupt factor (B) flag register D7–6 D5 D4 D3 D2 D1 D0 – FSTX1 FSRX1 FSERR1 FSTX0 FSRX0 FSERR0 reserved SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full SIF Ch.1 receive error SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full SIF Ch.0 receive error Setting – 1 Factor is generated 0 No factor is generated Init. R/W Remarks – X X X X X X – 0 when being read.
III PERIPHERAL BLOCK: SERIAL INTERFACE Register name Address Bit P0 function select register 00402D0 (B) D7 D6 D5 D4 D3 D2 D1 D0 Port SIO function extension register Name CFP07 CFP06 CFP05 CFP04 CFP03 CFP02 CFP01 CFP00 Function Setting P07 function selection P06 function selection P05 function selection P04 function selection P03 function selection P02 function selection P01 function selection P00 function selection 1 1 1 1 1 1 1 1 00402D7 D7–4 – D3 SSRDY3 reserved Serial I/F Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 SSOUT3: Serial I/F Ch.3 SOUT selection (D1) / Port SIO function extension register (0x402D7) Switches the function of pin P16/EXCL5/#DMAEND1/SOUT3. Write "1": SOUT3 Write "0": P16/EXCL5/#DMAEND1 Read: Valid To use the pin as SOUT3, set SSOUT3 (D1 / 0x402D7) to "1" and CFP16 (D6 / 0x402D4) to "0". To use the pin as P16, EXCL5, or #DMAEND1, set this bit to "0". At power-on, this bit is set to "0". SSCLK3: Serial I/F Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE SSCLK2: Serial I/F Ch.2 SCLK selection (D2) / Port SIO function extension register (0x402DB) Switches the function of pin P25/TM3/#SCLK2. Write "1": #SCLK2 Write "0": P25/TM3 Read: Valid To use the pin as #SCLK2, set SSCLK2 (D2 / 0x402DB) to "1" and CFP25 (D5 / 0x402D8) to "0". To use the pin as P25 or TM3, set this bit to "0". At power-on, this bit is set to "0". SSRDY2: Serial I/F Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 RXD07–RXD00: Ch.0 receive data (D[7:0]) / Serial I/F Ch.0 receive data register (0x401E1) RXD17–RXD10: Ch.1 receive data (D[7:0]) / Serial I/F Ch.1 receive data register (0x401E6) RXD27–RXD20: Ch.2 receive data (D[7:0]) / Serial I/F Ch.2 receive data register (0x401F1) RXD37–RXD30: Ch.3 receive data (D[7:0]) / Serial I/F Ch.3 receive data register (0x401F6) Stores received data.
III PERIPHERAL BLOCK: SERIAL INTERFACE PER0: Ch.0 parity-error flag (D3) / Serial I/F Ch.0 status register (0x401E2) PER1: Ch.1 parity-error flag (D3) / Serial I/F Ch.1 status register (0x401E7) PER2: Ch.2 parity-error flag (D3) / Serial I/F Ch.2 status register (0x401F2) PER3: Ch.3 parity-error flag (D3) / Serial I/F Ch.3 status register (0x401F7) Indicates whether a parity error occurred.
III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 RDBF0: Ch.0 receive data buffer full (D0) / Serial I/F Ch.0 status register (0x401E2) RDBF1: Ch.1 receive data buffer full (D0) / Serial I/F Ch.1 status register (0x401E7) RDBF2: Ch.2 receive data buffer full (D0) / Serial I/F Ch.2 status register (0x401F2) RDBF3: Ch.3 receive data buffer full (D0) / Serial I/F Ch.3 status register (0x401F7) Indicates the status of the receive data register (buffer).
III PERIPHERAL BLOCK: SERIAL INTERFACE EPR0: Ch.0 parity enable (D5) / Serial I/F Ch.0 control register (0x401E3) EPR1: Ch.1 parity enable (D5) / Serial I/F Ch.1 control register (0x401E8) EPR2: Ch.2 parity enable (D5) / Serial I/F Ch.2 control register (0x401F3) EPR3: Ch.3 parity enable (D5) / Serial I/F Ch.3 control register (0x401F8) Selects a parity function.
III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 SSCK0: Ch.0 input clock selection (D2) / Serial I/F Ch.0 control register (0x401E3) SSCK1: Ch.1 input clock selection (D2) / Serial I/F Ch.1 control register (0x401E8) SSCK2: Ch.2 input clock selection (D2) / Serial I/F Ch.2 control register (0x401F3) SSCK3: Ch.3 input clock selection (D2) / Serial I/F Ch.3 control register (0x401F8) Selects the clock source for an asynchronous transfer.
III PERIPHERAL BLOCK: SERIAL INTERFACE IRTL0: Ch.0 IrDA output logic inversion (D3) / Serial I/F Ch.0 IrDA register (0x401E4) IRTL1: Ch.1 IrDA output logic inversion (D3) / Serial I/F Ch.1 IrDA register (0x401E9) IRTL2: Ch.2 IrDA output logic inversion (D3) / Serial I/F Ch.2 IrDA register (0x401F4) IRTL3: Ch.3 IrDA output logic inversion (D3) / Serial I/F Ch.3 IrDA register (0x401F9) Inverts the logic of the IrDA output signal.
III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 ESERR0, ESRX0, ESTX0: Ch.0 interrupt enable (D0,D1,D2) / Serial I/F interrupt enable register (0x40276) ESERR1, ESRX1, ESTX1: Ch.1 interrupt enable (D3,D4,D5) / Serial I/F interrupt enable register (0x40276) Enable or disable interrupt generation to the CPU.
III PERIPHERAL BLOCK: SERIAL INTERFACE RSRX0, RSTX0: Ch.0 IDMA request (D6, D7) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA request register (0x40292) RSRX1, RSTX1: Ch.1 IDMA request (D0, D1) / Serial I/F Ch.1, A/D IDMA request register (0x40293) Specifies whether to invoke IDMA when an interrupt factor occurs.
III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 SIO2RS0: SIO Ch.2 receive-buffer full/FP1 interrupt factor switching (D1) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": SIO Ch.2 receive-buffer full Write "0": FP1 input Read: Valid Set to "1" to use the SIO Ch.2 receive-buffer full interrupt. Set to "0" to use the FP1 input interrupt. At power-on, this bit is set to "0". SIO3ES0: SIO Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE SIO3TS0: SIO Ch.3 transmit-buffer empty/FP6 interrupt factor switching (D6) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": SIO Ch.3 transmit-buffer empty Write "0": FP6 input Read: Valid Set to "1" to use the SIO Ch.3 transmit-buffer empty interrupt. Set to "0" to use the FP6 input interrupt. At power-on, this bit is set to "0".
III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 SIO3TS1: SIO Ch.3 transmit-buffer empty/TM16 Ch.4 compare A interrupt factor switching (D3) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. Write "1": SIO Ch.3 transmit-buffer empty Write "0": TM16 Ch.4 compare A Read: Valid Set to "1" to use the SIO Ch.3 transmit-buffer empty interrupt. Set to "0" to use the TM16 Ch.4 compare A interrupt. At power-on, this bit is set to "0". SIO2ES1: SIO Ch.2 receive error/TM16 Ch.
III PERIPHERAL BLOCK: SERIAL INTERFACE Programming Notes (1) Before setting various serial-interface parameters, make sure the transmit and receive operations are disabled (TXENx = RXENx = "0"). (2) When the serial interface is transmitting or receiving data, do not set TXENx or RXENx to "0", and do not execute the slp instruction. (3) In clock-synchronized transfers, the mode of communication is half-duplex, in which the clock line is shared between the transmit and receive units.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS A-1 III-9 INPUT/OUTPUT PORTS The Peripheral Block has a total of 42 input/output ports. Although each pin is used for input/output from/to the internal peripheral circuits, some pins can be used as general-purpose input/output ports unless they are used for the peripheral circuits. Input Ports (K Ports) Structure of Input Port The Peripheral Block contains 13 bits of input ports (K50 to K54, K60 to K67). Figure 9.1 shows the structure of a typical input port.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Input-Port Pins The input pins concurrently serve as the input pins for peripheral circuits, as shown in Table 9.1. Whether they are used as input ports or for peripheral circuits can be set bit-for-bit using a function select register. All pins not used for peripheral circuits can be used as general-purpose input ports that have an interrupt function. Table 9.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS A-1 I/O Memory of Input Ports Table 9.2 shows the control bits of the input ports. Table 9.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS I/O Ports (P Ports) Structure of I/O Port The Peripheral Block contains 29 bits of I/O ports (P00 to P07, P10 to P16, P20 to P27, P30 to P35) that can be directed for input or output through the use of a program. Figure 9.2 shows the structure of a typical I/O port.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Pin name P20/#DRD P21/#DWE/ #GAAS P22/TM0 P23/TM1 P24/TM2/ #SRDY2 P25/TM3/ #SCLK2 P26/TM4/ SOUT2 P27/TM5/SIN2 I/O I/O I/O P30/#WAIT/ #CE4&5 P31/#BUSGET/ #GARD P32/#DMAACK0 /#SRDY3 P33/#DMAACK1 /SIN3 P34/#BUSREQ/ #CE6 P35/#BUSACK I/O I/O I/O I/O I/O I/O I/O Pull-up Function – I/O port / #DRD output – I/O port / #DWE output / GA address strobe output (Ex) – I/O port / 16-bit timer 0 output – I/O port / 16-bit timer 1 output – I/O port / 16-bit timer 2 output / Ser
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS I/O Memory of I/O Ports Table 9.4 shows the control bits of the I/O ports. Table 9.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS A-1 Register name Address Port SIO function extension register Bit Name Function Setting 00402D7 D7–4 – D3 SSRDY3 reserved Serial I/F Ch.3 SRDY selection 1 #SRDY3 D2 SSCLK3 Serial I/F Ch.3 SCLK selection 1 #SCLK3 D1 SSOUT3 Serial I/F Ch.3 SOUT selection 1 SOUT3 D0 SSIN3 Serial I/F Ch.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Register name Address Bit Port function extension register D7 D6 D5 D4 D3 D2 D1 CFEX7 CFEX6 CFEX5 CFEX4 CFEX3 CFEX2 CFEX1 P07 port extended function P06 port extended function P05 port extended function P04 port extended function P31 port extended function P21 port extended function P10, P11, P13 port extended function D0 CFEX0 P12, P14 port extended function 00402DF (B) Name Function Setting 1 1 1 1 1 1 1 #DMAEND3 #DMAACK3 #DMAEND2 #DMAACK2 #GARD #GAAS
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS A-1 IOC07–IOC00: P0[7:0] port I/O control (D[7:0]) / P0 port I/O control register (0x402D2) IOC16–IOC10: P1[6:0] port I/O control (D[6:0]) / P1 port I/O control register (0x402D6) IOC27–IOC20: P2[7:0] port I/O control (D[7:0]) / P2 port I/O control register (0x402DA) IOC35–IOC30: P3[5:0] port I/O control (D[5:0]) / P3 port I/O control register (0x402DE) Directs an I/O port for input or output and indicates the I/O control signal value of the port.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS SSRDY3: Serial I/F Ch.3 SRDY selection (D3) / Port SIO function extension register (0x402D7) Switches the function of pin P32/#DMAACK0/#SRDY3. Write "1": #SRDY3 Write "0": P32/#DMAACK0 Read: Valid To use the pin as #SRDY3, set SSRDY3 (D3 / 0x402D7) to "1" and CFP32 (D2 / 0x402DC) to "0". To use the pin as P32 or #DMAACK0, set this bit to "0". At power-on, this bit is set to "0". SSIN2: Serial I/F Ch.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS A-1 CFEX0: P12, P14 function extension (D0) / Port function extension register (0x402DF) CFEX1: P10, P11, P13 function extension (D1) / Port function extension register (0x402DF) CFEX2: P21 function extension (D2) / Port function extension register (0x402DF) CFEX3: P31 function extension (D3) / Port function extension register (0x402DF) CFEX4: P04 function extension (D4) / Port function extension register (0x402DF) CFEX5: P05 function extension (D5) / Port function
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Input Interrupt The input ports and the I/O ports support eight system of port input interrupts and two systems of key input interrupts. Port Input Interrupt The port input interrupt circuit has eight interrupt systems (FPT7–FPT0) and a port can be selected for generating each interrupt factor. The interrupt condition can also be selected from between input signal edge and input signal level. Figure 9.3 shows the configuration of the port input interrupt circuit.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS A-1 Conditions for port input-interrupt generation Each port input interrupt can be generated by the edge or level of the input signal. The SEPTx bit of the edge/level select register (0x402C9) is used for this selection. When SEPTx is set to "1", the FPTx interrupt will be generated at the signal edge. When SEPTx is set to "0", the FPTx interrupt will be generated by the input signal level.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Key Input Interrupt The key input interrupt circuit has two interrupt systems (FPK1 and FPK0) and a port group can be selected for generating each interrupt factor. The interrupt condition can also be set by software. Figure 9.4 shows the configuration of the port input interrupt circuit.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS A-1 Selecting input pins For the FPK1 interrupt system, a four-bit input pin group can be selected from the four predefined groups. For the FPK0 system, a five-bit input pin group can be selected. Table 9.7 shows the control bits and the selectable groups for each factor. Table 9.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Since K50 is masked from interrupt by SMPK00, no interrupt occurs at that point (2) above. Next, because K53 becomes "0" at (3), an interrupt is generated due to the lack of a match between the data of the input pin K5[4:1] that is enabled for interrupt and that of the input comparison register SCPK0[4:1].
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS A-1 Table 9.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS I/O Memory for Input Interrupts Table 9.10 shows the control bits for the port input and key input interrupts. Table 9.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS A-1 Register name Address Bit Port input 4–7, 0040287 clock timer, A/D (B) interrupt factor flag register D7–6 D5 D4 D3 D2 D1 D0 Name Function – FP7 FP6 FP5 FP4 FCTM FADE reserved Port input 7 Port input 6 Port input 5 Port input 4 Clock timer A/D converter Setting Init. R/W – 1 Factor is generated 0 No factor is generated Remarks – X X X X X X – 0 when being read. R/W R/W R/W R/W R/W R/W Port input 0–3, high-speed DMA Ch.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Function Setting Key input 00402CA D7–4 – interrupt select (B) D3 SPPK11 register D2 SPPK10 D1 SPPK01 D0 SPPK00 Register name Address Bit Name reserved FPK1 interrupt input port selection – Key input interrupt (FPK0) input comparison register Init. R/W Remarks 11 10 01 00 P2[7:4] P0[7:4] K6[7:4] K6[3:0] FPK0 interrupt input port selection 11 10 01 00 P2[4:0] P0[4:0] K6[4:0] K5[4:0] – 0 0 0 0 – 0 when being read.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS A-1 SPPT7–SPPT0: Input polarity selection (D[7:0]) / Port interrupt input polarity select register (0x402C8) Selects input signal porarity for port interrupt generation. Write "1": High level or Rising edge Write "0": Low level or Falling edge Read: Valid SPPTx is the input polarity select bit corresponding to the FPTx interrupt. When SPPTx is set to "1", the FPTx interrupt will be generated by a high level input or at the rising edge.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS SMPK13–SMPK10: FPK1 input mask (D[3:0]) / FPK1 input mask register (0x402CF) SMPK04–SMPK00: FPK0 input mask (D[4:0]) / FPK0 input mask register (0x402CE) Sets conditions for key-input interrupt generation (interrupt enabled/disabled). Write "1": Interrupt enabled Write "0": Interrupt disabled Read: Valid SMPK is an input mask register for each key-input interrupt system. Interrupts for bits set to "1" are enabled, and interrupts for bits set to "0" are disabled.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS A-1 FP3–FP0: Port input 3–0 interrupt factor flag (D[3:0]) / Key input, port input 0–3 interrupt factor flag register (0x40280) FP7–FP4: Port input 7–4 interrupt factor flag (D[5:2]) / Port input 4–7, clock timer, A/D interrupt factor flag register (0x40287) FK1, FK0: Key input 1, 0 interrupt factor flag (D[5:4]) / Key input, port input 0–3 interrupt factor flag register (0x40280) Indicates the status of an input interrupt factor generated.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS RP3–RP0: Port input 3–0 IDMA request (D[3:0]) / Port input 0–3, high-speed DMA, 16-bit timer 0 IDMA request register (0x40290) RP7–RP4: Port input 7–4 IDMA request (D[7:4]) / Serial I/F Ch.1, A/D, Port input 4–7 IDMA request register (0x40293) Specifies whether to invoke IDMA when an interrupt factor occurs.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS A-1 Programming Notes (1) After an initial reset, the interrupt factor flags become indeterminate. To prevent generation of an unwanted interrupt or IDMA request, be sure to reset the flags in a program. (2) To prevent regeneration of interrupts due to the same factor following the occurrence of an interrupt, always be sure to reset the interrupt factor flag before resetting the PSR or executing the reti instruction.
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S1C33L03 FUNCTION PART IV ANALOG BLOCK
IV ANALOG BLOCK: INTRODUCTION A-1 IV-1 INTRODUCTION The analog block consists of an A/D converter with 8 input channels.
IV ANALOG BLOCK: INTRODUCTION THIS PAGE IS BLANK.
IV ANALOG BLOCK: A/D CONVERTER A-1 IV-2 A/D CONVERTER Features and Structure of A/D Converter The Analog Block contains an A/D converter with the following features: • Conversion method: Successive comparison • Resolution: 10 bits • Input channels: Maximum of 8 • Conversion time: Maximum of 10 µs (when a 2-MHz input clock is selected) • Conversion range: Between VSS and AVDDE • Two conversion modes can be selected: Normal mode: Conversion is completed in one operation.
IV ANALOG BLOCK: A/D CONVERTER I/O Pins of A/D Converter Table 2.1 shows the pins used by the A/D converter. Table 2.
IV ANALOG BLOCK: A/D CONVERTER A-1 Setting A/D Converter When the A/D converter is used, the following settings must be made before an A/D conversion can be performed: 1. Setting analog input pins 2. Setting the input clock 3. Selecting the analog-conversion start and end channels 4. Setting the A/D conversion mode 5. Selecting a trigger 6. Setting the sampling time 7. Setting interrupt/IDMA/HSDMA The following describes how to set each item.
IV ANALOG BLOCK: A/D CONVERTER Table 2.
IV ANALOG BLOCK: A/D CONVERTER A-1 Setting the sampling time The A/D converter contains ST[1:0] (D[1:0]) / A/D sampling register (0x40245) that allows the analog-signal input sampling time to be set in four steps (3, 5, 7, or 9 times the input clock period). However, this register should be used as set by default (ST = "11"; x9 clock periods). Control and Operation of A/D Conversion Figure 2.2 shows the operation of the A/D converter.
IV ANALOG BLOCK: A/D CONVERTER When a trigger is input, the A/D converter samples and A/D-converts the analog input signal, beginning with the conversion start channel selected by CS[2:0].
IV ANALOG BLOCK: A/D CONVERTER A-1 A/D Converter Interrupt and DMA Upon completion of A/D conversion in each channel, the A/D converter generates an interrupt and invokes the DMA if necessary.
IV ANALOG BLOCK: A/D CONVERTER Trap vector The A/D converter's interrupt trap-vector default address is set to 0x0C00100. The base address of the trap table can be changed using the TTBR register (0x48134 to 0x48137).
IV ANALOG BLOCK: A/D CONVERTER A-1 I/O Memory of A/D Converter Table 2.6 shows the control bits of the A/D converter. For details on the I/O memory of the prescaler used to set clocks, refer to "Prescaler". For details on the I/O memory of the programmable timers used for a trigger, refer to "8-Bit Programmable Timers" or "16-Bit Programmable Timers". Table 2.
IV ANALOG BLOCK: A/D CONVERTER Register name Address Bit Serial I/F Ch.1, 004026A A/D interrupt (B) priority register D7 D6 D5 D4 D3 D2 D1 D0 Name Function reserved A/D converter interrupt level – 0 to 7 reserved Serial interface Ch.
IV ANALOG BLOCK: A/D CONVERTER A-1 ADD9–ADD0: A/D converted data (D[1:0]) / A/D conversion result (high-order) register (0x40241) (D[7:0]) / A/D conversion result (low-order) register (0x40240) Stores the results of A/D conversion. The LSB is stored in ADD0, and the MSB is stored in ADD9. ADD0 and ADD1 are mapped to bits D0 and D1 at the address 0x40241, but bits D2 through D7 are always 0 when read. This is a read-only register, so writing to this register is ignored.
IV ANALOG BLOCK: A/D CONVERTER ADF: Conversion-complete flag (D3) / A/D enable register (0x40244) Indicates that A/D conversion has been completed. Read "1": Conversion completed Read "0": Being converted or standing by Write: Invalid This flag is set to "1" when A/D conversion is completed, and the converted data is stored in the data register and is reset to "0" when the converted data is read out.
IV ANALOG BLOCK: A/D CONVERTER A-1 ST1–ST0: Sampling-time setup (D[1:0]) / A/D sampling register (0x40245) Sets the analog input sampling time. Table 2.8 Sampling Time ST1 ST0 Sampling Time 1 1 9-clock period 1 0 7-clock period 0 1 5-clock period 0 0 3-clock period The A/D converter input clock is used for counting. At initial reset, ST is set to "11" (9-clock period). To maintain the conversion accuracy, use ST as set by default (9-clock period).
IV ANALOG BLOCK: A/D CONVERTER The interrupt factor flag is set to "1" whenever interrupt generation conditions are met, regardless of how the interrupt enable and interrupt priority registers are set.
IV ANALOG BLOCK: A/D CONVERTER A-1 Programming Notes (1) Before setting the conversion mode, start/end channels, etc. for the A/D converter, be sure to disable the A/D converter (ADE (D2) / A/D enable register (0x40244) = "0"). A change in settings while the A/D converter is enabled could cause it to operate erratically. (2) The A/D converter operates only when the prescaler is operating. When the A/D converter registers are set up, the prescaler must be operating.
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S1C33L03 FUNCTION PART V DMA BLOCK
V DMA BLOCK: INTRODUCTION A-1 V-1 INTRODUCTION The DMA Block is configured with two types of DMA controllers: HSDMA (High-Speed DMA) that has onchip registers for controlling DMA command information and IDMA (Intelligent DMA) that uses a memory area for storing DMA command information.
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V DMA BLOCK: HSDMA (High-Speed DMA) A-1 V-2 HSDMA (High-Speed DMA) Functional Outline of HSDMA The DMA Block contains four channels of HSDMA (High-Speed DMA) circuits that support dual-address transfer and single-address transfer methods. Since the control registers required for the DMA function are built into the chip, DMA requests for data transfer can be responded to instantaneously.
V DMA BLOCK: HSDMA (High-Speed DMA) I/O Pins of HSDMA Table 2.1 lists the I/O pins used for HSDMA. Table 2.
V DMA BLOCK: HSDMA (High-Speed DMA) A-1 Programming Control Information The HSDMA operates according to the control information set in the registers. Note that some control bits change their functions according to the address mode. The following explains how to set the contents of control information. Before using HSDMA, make each the settings described below. Setting the Registers in Dual-Address Mode Make sure that the HSDMA channel is disabled (HSx_EN = "0") before setting the control information.
V DMA BLOCK: HSDMA (High-Speed DMA) Block length When using block transfer mode (DxMOD = "10"), the data block length (in units of DATSIZEx) should be set using the BLKLENx[7:0] bits. BLKLEN0[7:0]: Ch. 0 block length (D[7:0]) / HSDMA Ch. 0 transfer counter register (0x48220) BLKLEN1[7:0]: Ch. 1 block length (D[7:0]) / HSDMA Ch. 1 transfer counter register (0x48230) BLKLEN2[7:0]: Ch. 2 block length (D[7:0]) / HSDMA Ch. 2 transfer counter register (0x48240) BLKLEN3[7:0]: Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) A-1 D0ADRL[15:0]: D1ADRL[15:0]: D2ADRL[15:0]: D3ADRL[15:0]: D0ADRH[11:0]: D1ADRH[11:0]: D2ADRH[11:0]: D3ADRH[11:0]: Ch. 0 destination address [15:0] (D[F:0]) / Ch. 0 low-order destination address set-up register (0x48228) Ch. 1 destination address [15:0] (D[F:0]) / Ch. 1 low-order destination address set-up register (0x48238) Ch. 2 destination address [15:0] (D[F:0]) / Ch. 2 low-order destination address set-up register (0x48248) Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) Setting the Registers in Single-Address Mode Make sure that the HSDMA channel is disabled (HSx_EN = "0") before seffing the control information. Address mode The address mode select bit DUALMx should be set to "0" (single-address mode). This bit is set to "0" at initial reset. Transfer mode A transfer mode should be set using the DxMOD[1:0] bits.
V DMA BLOCK: HSDMA (High-Speed DMA) A-1 In single-address mode, data transfer is performed between the memory connected to the system interface and an external I/O device. The I/O device is accessed directly by the #DMAACKx signal, so it is unnecessary to specify an address. DxADRL[15:0] and DxADRH[11:0] are not used in single-address mode. Address increment/decrement control The memory addresses can be incremented or decremented when one data transfer is completed. SxIN[1:0] is used to set this function.
V DMA BLOCK: HSDMA (High-Speed DMA) Trigger Factor A HSDMA tigger factor can be selected from among 13 types using the HSDMA trigger set-up register for each channel. This function is supported by the interrupt controller. HSD0S[3:0]: Ch. 0 trigger set-up (D[3:0]) / HSDMA Ch. 0/1 trigger set-up register (0x40298) HSD1S[3:0]: Ch. 1 trigger set-up (D[7:4]) / HSDMA Ch. 0/1 trigger set-up register (0x40298) HSD2S[3:0]: Ch. 2 trigger set-up (D[3:0]) / HSDMA Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) A-1 Operation of HSDMA An HSDMA channel starts data transfer by the selected trigger factor. Make sure that transfer conditions and a trigger factor are set and the HSDMA channel is enabled before starting a DMA transfer. Operation in Dual-Address Mode In dual-address mode, both the source and destination addresses are accessed according to the bus condition set by the BCU. HSDMA has three transfer modes, in each of which data transfer operates differently.
V DMA BLOCK: HSDMA (High-Speed DMA) Successive transfer mode The channel for which DxMOD in control information is set to "01" operates in successive transfer mode. In this mode, a data transfer is performed by one trigger a number of times as set by the transfer counter. The transfer counter is decremented to "0" by one transfer executed. The operation of HSDMA in successive transfer mode is shown by the flow chart in Figure 2.4.
V DMA BLOCK: HSDMA (High-Speed DMA) A-1 Block transfer mode The channel for which DxMOD in control information is set to "10" operates in block transfer mode. In this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by BLKLENx. If a block transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required.
V DMA BLOCK: HSDMA (High-Speed DMA) Operation in Single-Address Mode The operation of each transfer mode is almost the same as that of dual-address mode (see the previous section). However, data read/write operation is performed simultaneously in single-address mode. The following explains the data transfer operation different from dual-address mode.
V DMA BLOCK: HSDMA (High-Speed DMA) A-1 Timing Chart Dual-address mode (1) SRAM Example: When 2 (RD)/1 (WR) wait cycles are inserted Read cycle Write cycle source address destination address BCLK A[23:0] #CE(src) ;;; ;;; #CE(dst) #RD #WRH/#WRL #DMAEND Figure 2.
V DMA BLOCK: HSDMA (High-Speed DMA) Single-address mode (1) SRAM Example: When 2 (RD)/1 (WR) wait cycles are inserted BCLK ;;; ;;; addr A[23:0] #CExx #RD #WRH/#WRL #DMAACK #DMAEND Figure 2.
V DMA BLOCK: HSDMA (High-Speed DMA) A-1 Interrupt Function of HSDMA The DMA controller can generate an interrupt when the transfer counter in each HSDMA channel reaches 0. Furthermore, channels 0 and 1 can invoke IDMA using their interrupt factor. Control registers of the interrupt controller Table 2.3 shows the control registers of the interrupt controller that are provided for each channel. Table 2.3 Control Registers of Interrupt Controller Channel Ch. 0 Ch. 1 Ch. 2 Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) Intelligent DMA Intelligent DMA (IDMA) can be invoked by the end-of-transfer interrupt factor of channels 0 and 1 of HSDMA. The following shows the IDMA channels set in HSDMA: IDMA channel Channel 0 end-of-transfer interrupt: 0x05 Channel 1 end-of-transfer interrupt: 0x06 Before IDMA can be invoked, the corresponding bits of the IDMA request and IDMA enable registers must be set to "1". Settings of transfer conditions on the IDMA side are also required. Table 2.
V DMA BLOCK: HSDMA (High-Speed DMA) A-1 I/O Memory of HSDMA Table 2.5 shows the control bits of HSDMA. Table 2.5 Control Bits of HSDMA Register name Address Bit High-speed 0040263 DMA Ch.0/1 (B) interrupt priority register D7 D6 D5 D4 D3 D2 D1 D0 – PHSD1L2 PHSD1L1 PHSD1L0 – PHSD0L2 PHSD0L1 PHSD0L0 reserved High-speed DMA Ch.1 interrupt level – 0 to 7 reserved High-speed DMA Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) Register name Address Bit Name High-speed DMA Ch.0/1 trigger set-up register D7 D6 D5 D4 HSD1S3 HSD1S2 HSD1S1 HSD1S0 High-speed DMA Ch.1 trigger set-up D3 D2 D1 D0 HSD0S3 HSD0S2 HSD0S1 HSD0S0 High-speed DMA Ch.0 trigger set-up D7 D6 D5 D4 HSD3S3 HSD3S2 HSD3S1 HSD3S0 High-speed DMA Ch.3 trigger set-up D3 D2 D1 D0 HSD2S3 HSD2S2 HSD2S1 HSD2S0 High-speed DMA Ch.2 trigger set-up High-speed DMA Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) A-1 Register name Address Bit P1 function select register D7 D6 – CFP16 reserved P16 function selection D5 CFP15 P15 function selection D4 CFP14 P14 function selection D3 CFP13 P13 function selection D2 CFP12 P12 function selection D1 CFP11 P11 function selection D0 CFP10 P10 function selection D7 D6 D5 D4 D3 D2 D1 D0 – IOC16 IOC15 IOC14 IOC13 IOC12 IOC11 IOC10 reserved P16 I/O control P15 I/O control P14 I/O control P13 I/O control P12 I/O cont
V DMA BLOCK: HSDMA (High-Speed DMA) Register name Address Bit Name High-speed 0048222 DMA Ch.0 (HW) control register DF DE DUALM0 D0DIR DD–8 D7 D6 D5 D4 D3 D2 D1 D0 – TC0_H7 TC0_H6 TC0_H5 TC0_H4 TC0_H3 TC0_H2 TC0_H1 TC0_H0 Note: D) Dual address mode S) Single address mode High-speed 0048224 DMA Ch.0 (HW) low-order source address set-up register Note: D) Dual address mode S) Single address mode High-speed 0048226 DMA Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) A-1 Register name Address Bit Name High-speed 004822A DMA Ch.0 (HW) high-order destination address set-up register DF DE D0MOD1 D0MOD0 Ch.0 transfer mode DD DC D0IN1 D0IN0 D) Ch.0 destination address control S) Invalid DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D0ADRH11 D) Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) Register name Address Bit High-speed 0048234 DMA Ch.1 (HW) low-order source address set-up register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1ADRL15 D) Ch.1 source address[15:0] S1ADRL14 S) Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) A-1 Register name Address Bit Name High-speed 004823A DMA Ch.1 (HW) high-order destination address set-up register DF DE D1MOD1 D1MOD0 Ch.1 transfer mode DD DC D1IN1 D1IN0 D) Ch.1 destination address control S) Invalid DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D1ADRH11 D) Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) Register name Address Bit High-speed 0048244 DMA Ch.2 (HW) low-order source address set-up register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S2ADRL15 D) Ch.2 source address[15:0] S2ADRL14 S) Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) A-1 Register name Address Bit Name High-speed 004824A DMA Ch.2 (HW) high-order destination address set-up register DF DE D2MOD1 D2MOD0 Ch.2 transfer mode DD DC D2IN1 D2IN0 D) Ch.2 destination address control S) Invalid DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D2ADRH11 D) Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) Register name Address Bit High-speed 0048254 DMA Ch.3 (HW) low-order source address set-up register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S3ADRL15 D) Ch.3 source address[15:0] S3ADRL14 S) Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) A-1 Register name Address Bit Name High-speed 004825A DMA Ch.3 (HW) high-order destination address set-up register DF DE D3MOD1 D3MOD0 Ch.3 transfer mode DD DC D3IN1 D3IN0 D) Ch.3 destination address control S) Invalid DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D3ADRH11 D) Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) IOC16–IOC15: P1[6:5] port I/O control (D[6:5]) / P1 I/O control register (0x402D6) Directs P15 and P16 for input or output and indicates the I/O control signal value of the port. When writing data Write "1": Output mode Write "0": Input mode To use the #DMAEND0 pin (channel 0), direct the pin for output by writing "1" to IOC15; to use the #DMAEND1 pin (channel 1), direct the pin for output by writing "1" to IOC16.
V DMA BLOCK: HSDMA (High-Speed DMA) A-1 HSD0S3–HSD0S0: Ch. 0 trigger set-up (D[3:0]) / HSDMA Ch. 0/1 trigger set-up register (0x40298) HSD1S3–HSD1S0: Ch. 1 trigger set-up (D[7:4]) / HSDMA Ch. 0/1 trigger set-up register (0x40298) HSD2S3–HSD2S0: Ch. 2 trigger set-up (D[3:0]) / HSDMA Ch. 2/3 trigger set-up register (0x40299) HSD3S3–HSD3S0: Ch. 3 trigger set-up (D[7:4]) / HSDMA Ch. 2/3 trigger set-up register (0x40299) Select a trigger factor for each HSDMA channel. Table 2.6 HSDMA Trigger Factor Value Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) HS0_EN: Ch. 0 enable (D0) / HSDMA Ch. 0 enable register (0x4822C) HS1_EN: Ch. 1 enable (D0) / HSDMA Ch. 1 enable register (0x4823C) HS2_EN: Ch. 2 enable (D0) / HSDMA Ch. 2 enable register (0x4824C) HS3_EN: Ch. 3 enable (D0) / HSDMA Ch. 3 enable register (0x4825C) Enable a DMA transfer. Write "1": Enabled Write "0": Disabled Read: Valid DMA transfer is enabled by writing "1" to this bit.
V DMA BLOCK: HSDMA (High-Speed DMA) A-1 D0MOD1–D0MOD0: Ch. 0 transfer mode (D[F:E]) / Ch. 0 high-order destination address set-up register (0x4822A) D1MOD1–D1MOD0: Ch. 1 transfer mode (D[F:E]) / Ch. 1 high-order destination address set-up register (0x4823A) D2MOD1–D2MOD0: Ch. 2 transfer mode (D[F:E]) / Ch. 2 high-order destination address set-up register (0x4824A) D3MOD1–D3MOD0: Ch. 3 transfer mode (D[F:E]) / Ch. 3 high-order destination address set-up register (0x4825A) Select a transfer mode. Table 2.
V DMA BLOCK: HSDMA (High-Speed DMA) D0IN1–D0IN0: Ch. 0 destination address control (D[D:C]) / Ch. 0 high-order destination address set-up register (0x4822A) D1IN1–D1IN0: Ch. 1 destination address control (D[D:C]) / Ch. 1 high-order destination address set-up register (0x4823A) D2IN1–D2IN0: Ch. 2 destination address control (D[D:C]) / Ch. 2 high-order destination address set-up register (0x4824A) D3IN1–D3IN0: Ch. 3 destination address control (D[D:C]) / Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) A-1 S0ADRL15–S0ADRL0: Ch. 0 source address[15:0] (D[F:0]) / Ch. 0 low-order source address set-up register (0x48224) S0ADRH11–S0ADRH0: Ch. 0 source address[27:16] (D[B:0]) / Ch. 0 high-order source address set-up register (0x48226) S1ADRL15–S1ADRL0: Ch. 1 source address[15:0] (D[F:0]) / Ch. 1 low-order source address set-up register (0x48234) S1ADRH11–S1ADRH0: Ch. 1 source address[27:16] (D[B:0]) / Ch.
V DMA BLOCK: HSDMA (High-Speed DMA) EHDM0: Ch. 0 interrupt enable (D0) / DMA interrupt enable register (0x40271) EHDM1: Ch. 1 interrupt enable (D1) / DMA interrupt enable register (0x40271) EHDM2: Ch. 2 interrupt enable (D2) / DMA interrupt enable register (0x40271) EHDM3: Ch. 3 interrupt enable (D3) / DMA interrupt enable register (0x40271) Enable or disable interrupt generation to the CPU.
V DMA BLOCK: HSDMA (High-Speed DMA) A-1 RHDM0: Ch.0 IDMA request (D4) / Port input 0–3, HSDMA, 16-bit timer 0 IDMA request register (0x40290) RHDM1: Ch.1 IDMA request (D5) / Port input 0–3, HSDMA, 16-bit timer 0 IDMA request register (0x40290) Specify whether IDMA need to be invoked when an interrupt factor occurs.
V DMA BLOCK: HSDMA (High-Speed DMA) Programming Notes (1) When setting the transfer conditions, always make sure the DMA controller is inactive (HSx_EN = "0"). (2) After an initial reset, the interrupt factor flag (FHDMx) becomes indeterminate. Always be sure to reset the flag to prevent interrupts or IDMA requests from being generated inadvertently.
V DMA BLOCK: IDMA (Intelligent DMA) A-1 V-3 IDMA (Intelligent DMA) Functional Outline of IDMA The DMA Block contains an intelligent DMA (IDMA), a function that allows control information to be programmed in RAM. Up to 128 channels can be programmed, including 31 channels that are invoked by an interrupt factor that occurs in some internal peripheral circuit.
V DMA BLOCK: IDMA (Intelligent DMA) The contents of control information (3 words) in each channel are shown in the table below. Table 3.
V DMA BLOCK: IDMA (Intelligent DMA) BLKLEN[7:0]: Block size/transfer counter (D[7:0]/1st Word) In block transfer mode, set the size of a block that is transferred in one operation (in units of DATSIZ). In single transfer and successive transfer modes, set an 8-bit low-order value for the transfer count here. A-1 Note: The transfer count and block size thus set are decremented according to the transfers performed.
V DMA BLOCK: IDMA (Intelligent DMA) DSINC[1:0]: Destination address control (D[29:28]/3rd Word) Set the destination address update format. If the format is set for "address fixed" (00), the destination address is not changed by the performance of a data transfer operation. Even when transferring multiple data, the transfer data is always written to the same address.
V DMA BLOCK: IDMA (Intelligent DMA) A-1 IDMA Invocation The triggers by which IDMA is invoked have the following three causes: 1. Interrupt factor in an internal peripheral circuit 2. Trigger in the software application 3. Link setting Enabling/disabling DMA transfer The IDMA controller is enabled by writing "1" to the IDMA enable bit IDMAEN (D0) / IDMA enable register (0x48205), and is ready to accept the triggers described above.
V DMA BLOCK: IDMA (Intelligent DMA) These interrupt factors are used in common for interrupt requests and IDMA invocation requests. To invoke IDMA upon the occurrence of an interrupt factor, set the corresponding bits of the IDMA request and IDMA enable registers shown in the table by writing "1". Then when an interrupt factor occurs, an interrupt request to the CPU is kept pending and the corresponding IDMA channel is invoked.
V DMA BLOCK: IDMA (Intelligent DMA) A-1 IDMA invocation request during a DMA transfer An IDMA invocation request to another channel that is generated during a DMA transfer is kept pending until the DMA transfer that was being executed at the time is completed. Since an invocation request is not cleared, new requests will be accepted when the DMA transfer under execution is completed.
V DMA BLOCK: IDMA (Intelligent DMA) Operation of IDMA IDMA has three transfer modes, in each of which data transfer operates differently. Furthermore, an interrupt factor is processed differently depending on the type of trigger. The following describes the operation of IDMA in each transfer mode and how an interrupt factor is processed for each type of trigger. Single transfer mode The channels for which DMOD in control information is set to "00" operate in single transfer mode.
V DMA BLOCK: IDMA (Intelligent DMA) A-1 Successive transfer mode The channels for which DMOD in control information is set to "01" operate in successive transfer mode. In this mode, a data transfer is performed by one trigger a number of times as set by the transfer counter. The transfer counter is decremented to "0" by one transfer executed. The operation of IDMA in successive transfer mode is shown by the flow chart in Figure 3.2.
V DMA BLOCK: IDMA (Intelligent DMA) Block transfer mode The channels for which DMOD in control information is set to "10" operate in block transfer mode. In this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by BLKLEN. If a block transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. The operation of IDMA in block transfer mode is shown by the flow chart in Figure 3.3.
V DMA BLOCK: IDMA (Intelligent DMA) A-1 Processing of interrupt factors by type of trigger • When invoked by an interrupt factor The interrupt factor flag by which IDMA has been invoked remains set even during a DMA transfer. If the transfer counter is decremented to 0 and DINTEN = "1" (interrupt enabled) when one DMA transfer is completed, the interrupt factor that has invoked IDMA is not reset and an interrupt request is generated. At the same time, the IDMA request register is cleared to "0".
V DMA BLOCK: IDMA (Intelligent DMA) Linking If the IDMA channel number to be executed next is set in the IDMA link field "LNKCHN" of control information and LNKEN is set to "1" (link enabled), DMA successive transfer in that IDMA channel can be performed. An example of link setting is shown in Figure 3.6. Trigger After transfer Ch.3 Ch.5 Ch.
V DMA BLOCK: IDMA (Intelligent DMA) A-1 Interrupt Function of Intelligent DMA IDMA can generate an interrupt that causes invocation of IDMA and an interrupt for the completion of IDMA transfer itself.
V DMA BLOCK: IDMA (Intelligent DMA) Trap vector The trap vector address for an interrupt upon completion of IDMA transfer by default is set to 0x0C00068. The trap table base address can be changed using the TTBR registers (0x48134 to 0x48137). I/O Memory of Intelligent DMA Table 3.3 shows the control bits of IDMA. Table 3.
V DMA BLOCK: IDMA (Intelligent DMA) A-1 DBASEL[15:0]: IDMA base address [15:0] (D[F:0]) / IDMA base address low-order register (0x48200) DBASEH[11:0]: IDMA base address [27:16] (D[B:0]) / IDMA base address high-order register (0x48202) Specify the starting address of the control information to be placed in RAM. Use DBASEL to set the 16 low-order bits of the address and DBASEH to set the 12 high-order bits. The address to be set in these registers must always be a word (32-bit) boundary address.
V DMA BLOCK: IDMA (Intelligent DMA) FIDMA: IDMA interrupt factor flag (D4) / DMA interrupt factor flag register (0x40281) Indicate the occurrence status of an IDMA interrupt request.
V DMA BLOCK: IDMA (Intelligent DMA) A-1 Programming Notes (1) Before setting the IDMA base address, be sure to disable DMA transfers (IDMAEN = "0"). Writing to the IDMA base address register is ignored when the DMA transfer is enabled (IDMAEN = "1"). Also, when the register is read during a DMA transfer, the data is indeterminate. When setting or rewriting control information for each channel, make sure that DMA transfers will not occur in any channel.
V DMA BLOCK: IDMA (Intelligent DMA) THIS PAGE IS BLANK.
S1C33L03 FUNCTION PART VI SDRAM CONTROLLER BLOCK
VI SDRAM CONTROLLER BLOCK: INTRODUCTION A-1 VI-1 INTRODUCTION The SDRAM controller block provides a SDRAM interface that allows direct connection of external SDRAM chips via the BCU.
VI SDRAM CONTROLLER BLOCK: INTRODUCTION THIS PAGE IS BLANK.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 VI-2 SDRAM INTERFACE The SDRAM controller allows up to 32MB of SDRAM to be connected directly to areas 7 and 8 or areas 13 and 14. This chapter describes how to control the SDRAM interface, and how it operates. For the conditions and parameters used to configure the external bus except for the SDRAM interface, refer to Chapter II-4, "BCU (Bus Control Unit)".
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE I/O Pins and Connection I/O Pins Table 2.1 lists the pins used for the SDRAM interface. Table 2.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 S1C33 128M SDRAM (2M x 16 bits x 4 banks) SDA11(A12) SDA10(P33) SDA[9:0](A[10:1]) SDBA[1:0](A[15:14]) D[15:0] A11 A10 A[9:0] BA[1:0] DQ[15:0] BCLK SDCKE(P20) #SDCE0(#CE7) #SDCE1(#CE8) #SDCAS(#HCAS) #SDRAS(#LCAS) #SDWE(P21) HDQM(P32) LDQM(P15) CLK CKE #CS #CAS #RAS #WE DQMU DQML 128M SDRAM (2M x 16 bits x 4 banks) A11 A10 A[9:0] BA[1:0] DQ[15:0] CLK CKE #CS #CAS #RAS #WE DQMU DQML Figure 2.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE Notes: • Because the SDRAM address bus pins differ in bit numbers from ordinary external address pin names, care must be taken when connecting an SDRAM to the S1C33. (SDRAM address SDA0 is output from the A1 pin, and SDA12 is output from the A13 pin.) Furthermore, the SDA10 signal with a special function is assigned to the P33 pin, and not to the address bus A11. • If designated pins (e.g.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 SDRAM Controller Configuration Setting PLL When using the SDRAM controller, always enable the PLL. Refer to "PLL" in Section II-6, "CLG (Clock Generator)", for setting the PLL. The following shows the operating range of the SDRAM controller when the PLL is enabled. #X2SPD pin = "1" (x1 speed mode): 25 MHz max. (CPU operating frequency = 25 MHz), voltage 3.3±0.3 V #X2SPD pin = "0" (x2 speed mode): 17.5 MHz max. (CPU operating frequency = 20 MHz), voltage 3.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE B. When using areas 13/14 (CEFUNC = "01") B-1. A14IO (DD)/Access control register (0x48132) = "1" This sets areas 13/14 for internal access. B-2. A14WT[2:0] (D[2:0])/Areas 14–13 set-up register (0x48122) = "000" This sets areas 13/14 for no-wait access. B-3.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 Memory Configuration Use the registers described below to select the area in which SDRAMs are connected and the chip enable output pin to be used for SDRAMs. Selecting areas Area 7 or 13: SDRAR0 (D7)/SDRAM area configuration register (0x39FFC0) Area 8 or 14: SDRAR1 (D6)/SDRAM area configuration register (0x39FFC0) Writing "1" to SDRARx sets the corresponding area for SDRAM use.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE Bank, row, and column address configuration An SDRAM memory array consists of two or four banks, with each bank divided into pages. For this reason, SDRAMs have a bank select pin which is not found in asynchronous DRAMs. Inside the Bank, the Column (Page) address and the Row address are selected by #CAS and #RAS, respectively, in the same way as with asynchronous DRAMs.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 Selecting initialization sequence The SDRAM command sequence that is run immediately after SDRAM power-up can be selected to suit the specifications of the SDRAM used. For this setting, use the SDRIS (D4)/SDRAM control register (0x39FFC1). SDRIS = "0": 1. Precharge → 2. Refresh → 3. Mode Register Set SDRIS = "1": 1. Precharge → 2. Mode Register Set → 3. Refresh If no problems are incurred in either setting, SDRIS = "1" is recommended.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE Enabling/disabling bank interleaved access A bank cannot be accessed at the same time it is being precharged, so another bank may be accessed during that period, which results in increased access speed. For this purpose, the SDRAM controller supports a feature known as Bank Interleaved Access. Specify whether or not to use this feature with the SDRBI (D5)/SDRAM advanced control register (0x39FFC9).
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 Timing setup The following parameters can be set in conformity with SDRAM specifications before use. Table 2.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE SDRAM Operation Synchronous Clock The SDRAM controller uses the BCLK pin as it outputs the SDRAM clock. To CPU #X2SPD pin PLLS[1:0] pins Bus clock CLKDT[1:0] CLKCHG CLG High-speed (OSC3) oscillation circuit BCU OSC3_CLK A 1/1–1/8 CPU_CLK BCLKSEL[1:0] 1/1 or 1/2 PLL_CLK PLL BCU_CLK CPU_CLK OSC3_CLK PLL_CLK SDRENA BCLK pin SDRAMC Low-speed (OSC1) oscillation circuit 1/1 or 1/2 SD_CLK Refresh counter Figure 2.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 Power-up and Initialization The following describes the processing sequence for powering up the SDRAM. 1. Setting the BCU and SDRAM access conditions Set the BCU and the SDRAM controller as explained in "SDRAM Configuration". 2. SDRENA (D7)/SDRAM control register (0x39FFC1) = "1" This causes the pins shown in Table 2.1 to be switched for SDRAM signal use.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE SDRAM power VCC(Min.) BCLK NOP Command PALL MRS REF REF CMD H SDCKE #SDCEx #SDRAS #SDCAS #SDWE H HDQM/LDQM SDRENA bit SDRIS bit SDRINI bit SDRMRS bit Internal #WAIT SDA10 Valid Valid SDBA[1:0] Valid Valid SDA[12:11, 9:0] Valid Valid 100 µs min. tRP tRSC tRC tRC Figure 2.10 SDRAM Power-up and Initialization SDRAM Commands The SDRAM is controlled by commands that are comprised of a combination of high or low logic level signals. Table 2.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 Burst Read Cycle Except when the burst length is set to 1 (SDRBL[1:0] ≠ "00"), the SDRAM controller always reads data from the SDRAM in bursts. Figure 2.11 shows several examples of timing charts when reading out 4-word data from the same row address in varying burst lengths.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE Figure 2.12 shows an example of a timing chart in cases where the row address is varied during burst read. BCLK Command NOP SDCKE PRE NOP ACTV NOP READ NOP PRE NOP ACTV NOP READ NOP H #SDCEx #SDRAS #SDCAS #SDWE SDBA[1:0] BA BA BA SDA[10] ROW1 SDA[12:11, 9:0] ROW1 BA BA BA ROW2 COLn ROW2 COL0 LDQM/HDQM DQ[15:0] D(n) tRP tRCD D(n+1) D(n+2) D(0) tRP CAS latency =2 tRCD D(1) D(2) CAS latency =2 tRAS Figure 2.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 Refresh Mode The SDRAM controller supports two SDRAM refresh modes: auto refresh and self-refresh. Auto refresh The SDRAM controller incorporates a 12-bit auto refresh counter. This counter continues counting on OSC3 clock edges, and when a specified count is reached, commands are sent to the SDRAM that precharges and auto-refreshes all banks. The counter is reset at that time, and starts counting for the next refresh period.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE Self refresh Self-refresh uses the SDRAM’s self-refresh function and does not require clock pulses during the refresh period, thus helping to reduce the chip’s power consumption. This self-refresh function is also used for data retention during power-down mode. To cause the SDRAM to be self-refreshed, set the SDRSRF (D5)/SDRAM control register (0x39FFC1) to "1".
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 Power-down Mode The SDRAM controller supports three power-down modes for the S1C33 Core (HALT, HALT2, and SLEEP). In HALT mode, the bus clock is not turned off. Therefore, this mode can be set at any time. In HALT2 and SLEEP modes, the SDRAM’s auto-refresh function is disabled. Therefore, the SDRAM must be placed in self-refresh mode before entering HALT2 or SLEEP mode, by following the procedure described below. 1.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE 1. The device acting as the external bus master prompts the S1C33 to be prepared to release the bus by means of an interrupt or some other means. 2. When the S1C33 becomes ready to release the bus, it sets SDRSRF (D5/0x39FFC1) to "1" to place the SDRAM in self-refresh mode. The S1C33 should stop accessing the SDRAM thereafter. 3. After the SDRAM is placed in self-refresh mode, the external device outputs a bus request. 4.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 I/O Memory of SDRAM Interface Table 2.12 shows the control bits of the SDRAM interface. These registers are mapped into area 6 (0x39FFC0 to 0x39FFCA). Table 2.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE Register name Address SDRAM timing set-up register 2 Bit Name Function 039FFC5 D7–6 SDRTRCD1 SDRAM tRCD spec (B) SDRTRCD0 0 0 0 R/W R/W – – – 0 to 4096 – 1 1 1 1 1 1 1 1 1 1 1 1 – 0 when being read. R/W – 2 to 15 – 1 1 1 1 – 0 when being read. R/W This register must not be set less than "0x02". reserved – 1 8 bits 0 16 bits SDRAM data path bit width SDRAM bank interleaved access 1 Interleaved 0 One bank – reserved – 0 0 – – 0 when being read.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 Register name Address Bit Areas 14–13 0048122 set-up register (HW) DF–9 D8 D7 D6 D5 D4 Areas 8–7 0048128 set-up register (HW) Name Function Setting – A14DRA A13DRA A14SZ A14DF1 A14DF0 reserved Area 14 DRAM selection Area 13 DRAM selection Areas 14–13 device size selection Areas 14–13 output disable delay time – 0 0 0 1 1 – 0 when being read.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE Register name Address Bit Bus control register DF DE DD DC DB DA RBCLK – RBST8 REDO RCA1 RCA0 D9 D8 D7 D6 D5 RPC2 RPC1 RPC0 RRA1 RRA0 D4 D3 D2 D1 D0 – SBUSST SEMAS SEPD SWAITE 004812E (HW) Name Function BCLK output control reserved Burst ROM burst mode selection DRAM page mode selection Column address size selection B-VI-2-24 0 Enabled Remarks R/W – Writing 1 not allowed. R/W R/W R/W 0 0 0 0 0 R/W R/W R/W R/W 0 0 0 0 0 – Writing 1 not allowed.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 A14SZ: Areas 14–13 device size selection (D6) / Areas 14–13 set-up register (0x48122) A8SZ: Areas 8–7 device size selection (D6) / Areas 8–7 set-up register (0x48128) Select the size of the device connected to each area. Write "1": 8 bits Write "0": 16 bits Read: Valid Set the device size of the area used for an SDRAM in the same manner as that specified for SDRSZ (D6/0x39FFC9). At cold start, these bits are set to "0" (16 bits).
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE CEFUNC1–CEFUNC0: #CE pin function selection (D[A:9]) / DRAM timing set-up register (0x48130) Select an area for connection with an SDRAM. Table 2.14 #CE Output Assignment Pin #CE7/#SDCE0 #CE8/#SDCE1 CEFUNC = "00" #CE7/#SDCE0 #CE8/#SDCE1 CEFUNC = "01" CEFUNC = "1x" #CE13/#SDCE0 #CE13/#SDCE0 #CE14/#SDCE1 #CE14/#SDCE1 (Default: CEFUNC = "00") Set CEFUNC = "00" to use areas 7/8 for SDRAMs or CEFUNC = "01" to use areas 13/14 for SDRAMs.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 SDRPC1: #CE8/14 pin configuration (D2) / SDRAM area configuration register (0x39FFC0) SDRPC0: #CE7/13 pin configuration (D3) / SDRAM area configuration register (0x39FFC0) Set the chip-enable pin for an SDRAM. Write "1": #SDCEx (for SDRAM) Write "0": #CExx (for other devices) Read: Valid Select the pin to be used as a chip enable for the SDRAM connected to the S1C33. Write "1" to SDRPC0 to set the #CE7/13 pin for SDRAM use (#SDCE0).
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE SDRIS: Initial command sequence (D4) / SDRAM control register (0x39FFC1) Select the SDRAM initialization sequence. Write "1": 1. Precharge → 2. Mode Register Set → 3. Refresh Write "0": 1. Precharge → 2. Refresh → 3. Mode Register Set Read: Valid In accordance with the specifications of the SDRAM, select a sequence to determine the order the commands are sent to initialize the SDRAM. Initialization of the SDRAM is initiated by writing "1" to SDRINI (D6/0x39FFC1).
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 SDRBA: Number of SDRAM banks (D1) / SDRAM address configuration register (0x39FFC2) Set the number of banks of the SDRAM. Write "1": 4 banks Write "0": 2 banks Read: Valid Set "1" when a SDRAM configured with 4 banks is used or set "0" when a SDRAM configured with 2 banks is used. The contents set here are applied to all of areas 7, 8, 13, and 14 that are set for SDRAM. At cold start, SDRBA is set to "0" (2 banks).
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE SDRTRCD1–SDRTRCD0: SDRAM tRCD spec (D[7:6]) / SDRAM timing set-up register 2 (0x39FFC5) Set the tRCD SDRAM parameter (ACTIVE to READ or WRITE delay time). In accordance with the specifications of the SDRAM, specify this parameter in terms of the number of SDRAM clock cycles. Specifying 1–3 sets the period to 1–3 clock cycles. Specifying 0 sets the period to 4 clock cycles. At cold start, SDRTRCD is set to "00" (4).
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 SDRSZ: SDRAM data path bit width (D6) / SDRAM advanced control register (0x39FFC9) Select the SDRAM data-path bit width. Write "1": 8 bits Write "0": 16 bits Read: Valid Set SDRSZ to "1" to use an 8-bit SDRAM or to "0" to use a 16-bit SDRAM. At cold start, SDRSZ is set to "0" (16 bits). At hot start, SDRSZ retains its status before being initialized.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE Programming Notes (1) Make sure that two wait cycles are inserted when accessing area 6, where the SDRAM controller is allocated. With any other number of specified wait cycles, data may not be written normally to the SDRAM control registers. (2) Set the area used for an SDRAM for internal access (A8IO (DA/0x48132) = "1" or A14IO (DD/0x48132) = "1").
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 Examples of SDRAM Controller Initialization Program The following shows examples of the initialization program for using SDRAM.
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE ;;; SDRAM auto refresh count high-order register xld.w %r0,0x39FFC7 ; xld.w %r1,0x00 ; ld.b [%r0],%r1 ; ;/////////////////////////////////////////// ;;; SDRAM self refresh count register ;;; xld.w %r0,0x39FFC8 ; ;;; xld.w %r1,0x0f ; ;;; ld.b [%r0],%r1 ; ;/////////////////////////////////////////// ;;; SDRAM advanced control register xld.w %r0,0x39FFC9 ; xld.w %r1,0x20 ; data width -> 16bit, bank interleave -> on ld.
S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK
VII LCD CONTROLLER BLOCK: INTRODUCTION A-1 VII-1 INTRODUCTION The LCD Controller Block provides LCD control signals for a 4- or 8-bit color/monochrome LCD panel.
VII LCD CONTROLLER BLOCK: INTRODUCTION THIS PAGE IS BLANK.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 VII-2 LCD CONTROLLER This section describes the functions and control procedures of the LCD controller. For details on setting the external display memory bus conditions and parameters, refer to Section II-4, "BCU (Bus Control Unit)", and Section VI-2, "SDRAM Interface". Overview Features The features of the LCD controller (LCDC) are described below.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER Power save • DOZE mode suitable for Epson’s self-refresh-type LCD panels • The status of the LCD controller can be checked using the power-save status bit.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 Block Diagram User logic signals Bus interface Address[23:0] Data[15:0] #CE6 #BUSREQ #BUSACK #BUSGET #CE7/13(8/14) FIFO Display pipeline Look-up table DMA interface Sequence controller Frame rate modulation LCD interface FPDAT[7:0] FPFRAME FPLINE FPSHIFT DRDY LCDPWR Control registers To SDRAM Controller Figure 2.1 Block Diagram of the LCD Controller Bus interface The LCD controller is mapped into area 6, along with the SDRAM controller.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER I/O Pins of the LCD Controller Table 2.1 lists the input/output pins of the LCD controller. Table 2.2 shows the pin configurations classified by type of LCD panel. Table 2.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 System Settings Setting the BCU The control registers of the LCD controller are mapped into area-6 addresses 0x39FFE0 to 0x39FFFF. Therefore, in order for the control registers to be accessed, the BCU must be set up in accordance with the procedure described below. 1. A6IO (D9)/access control register (0x48132) = "1" This sets area 6 so that the internal device will be accessed. 2.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER Use the EDMAEN (D3)/LCDC system control register (0x39FFFD) to mask the #DMAREQx signals. EDMAEN = "1": External DMA requests enabled EDMAEN = "0": External DMA requests disabled (default) Use the BREQEN (D2)/LCDC system control register (0x39FFFD) to mask the #BUSREQ signals.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 Clock The LCD controller uses the BCU clock as the source clock for its pixel clock PCLK and display memory clock MCLK. The maximum clock frequency that can be supplied to the LCD controller is 25 MHz. The BCU clock divide ratios can be set using the LCLKSEL[2:0] (D[2:0])/FIFO control register (0x39FFF4), as shown in Table 2.3 below.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER Setting the LCD Panel Types of Panels The LCD controller supports the following types of single-LCD panels. • 4- or 8-bit monochrome passive LCD panel • 4- or 8-bit color passive LCD panel Dual panels are not supported. The type of LCD panel used must be set in the LCD controller in advance, using the control bits described below.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 Display Modes The number of gray levels in grayscale display and the number of colors in color display are determined by the number of bits representing each pixel (bpp = bits per pixel). Write this bpp value to BPP[1:0] (D[7:6])/LCDC mode register 1 (0x39FFE2) in order to set the display mode (number of gray levels/colors displayed). Table 2.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER (3) 4-bpp (16-gray-level/16-color) mode One pixel is represented by 4 bits, displayed in 16 gray levels or 16 colors. For monochrome LCD panels, 16-gray-level display can be obtained by assigning 16 gray levels, including black and white, to 16 entries in the green look-up table (one each for bits = "0000" to "1111").
VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 Look-up Tables The LCD controller contains a look-up table consisting of 16 4-bit entries, one for each of the RGB color elements (red, green, and blue). Red look-up table Pixel data The pixel data selects an LUT entry.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER Grayscale-mode look-up tables In grayscale mode, the LCD controller uses only the green look-up table. For display in grayscale mode, select the data to be written to the look-up table from the 16 gray levels represented by 4 bits. The data 0x0, 0x1, 0x8, and 0xF represent black, 93.75% gray, 50% gray, and white, respectively. The differences in configuration between display modes are shown below.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER (3) 4-bpp (16-gray-level) mode Use all entries of the green look-up table. All 16 gray levels can be assigned to the look-up table. The data in entry 0 is output for pixel data "0x0", and the data in entry 15 is output for pixel data "0xF".
VII LCD CONTROLLER BLOCK: LCD CONTROLLER Color-mode look-up tables In color mode, the LCD controller uses the red (R), green (G), and blue (B) look-up tables. Each color element is represented by 4-bit data. RGB = 000 is black, RGB = F00 is red, RGB = 080 is 50% luminance green, RGB = F0F is magenta, RGB = FFF is white, and so on. In this way, colors are determined by the proportions of the three color elements.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER (2) 2-bpp (4-color) mode Use the first four entries of each look-up table. Select 4-color data from among the 4,096 colors, and write it to the respective entries. The RGB data in entry 0 is output for pixel data "00", and the RGB data in entry 3 is output for pixel data "11".
VII LCD CONTROLLER BLOCK: LCD CONTROLLER (3) 4-bpp (16-color) mode Use all entries of each look-up table. Select 16-color data from among the 4,096 colors, and write it to the respective entries. The RGB data in entry 0 is output for pixel data "0x0", and the RGB data in entry 15 is output for pixel data "0xF".
VII LCD CONTROLLER BLOCK: LCD CONTROLLER (4) 8-bpp (256-color) mode One pixel is represented by 8 bits, displayed in 256 colors. This mode is not available for grayscale display. In this mode, 256 discrete combinations are configured using eight entries in each of the red and green lookup tables, and four entries in the blue look-up table.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER Setting data in the look-up tables To set data in the look-up tables, use the look-up-table address register (0x39FFF5) and the look-up-table data register (0x39FFF7). Follow the procedure specified below in programming. 1. To the look-up-table address register (0x39FFF5), write the index (address) at which setting is to be started. When programming newly, write 0x0. When reading or writing to this register, be sure to access it bytewise.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 Frame Rates The frame rate is calculated from the LCD panel’s resolution, non-display period, and pixel clock frequency, as shown below. fPCLK Frame rate = ———————————————— (HDP + HNDP) × (VDP + VNDP) fPCLK: PCLK frequency (Hz) This is the input clock frequency for the LCD controller derived by dividing the BCU clock. The BCU-clock division ratio can be set to 1/1, 1/2, 1/3, or 1/4 using the LCLKSEL[2:0] (D[2:0])/FIFO control register (0x39FFF4).
VII LCD CONTROLLER BLOCK: LCD CONTROLLER Other Settings FPSHIFT mask When a color passive LCD panel is used, FPSHIFT (shift clock) can be turned on or off during the nondisplay period using FPSMASK (D2)/LCDC mode register 0 (0x39FFE1). FPSMASK = "1": Turned off FPSMASK = "0": Turned on (default) FPSMASK can only be set when LDCOLOR (D5)/LCDC mode register 0 (0x39FFE1) = "1" (color panel). Otherwise, FPSMASK has no effect.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 Display Control Controlling LCD Power Up/Down The LCD controller is activated to start up and generate LCD signals by setting LCDCEN (D5)/LCDC mode register 2 (0x39FFE3) to "1". Setting LCDCEN to "0" causes the LCD controller to stop operating, with the LCD signal output dropped low. For the LCD controller to start display correctly, the LCD-panel parameters and display data must be set before LCDCEN is set to "1".
VII LCD CONTROLLER BLOCK: LCD CONTROLLER The following is the power-down procedure. 1. Place the LCD controller in power-save mode (LPSAVE = "0b00"). 2. The LCD controller starts a power-down sequence and turns off the power to the LCD panel a one-frame period later, then pulls LCD signals low. 3. Because the bus clock is turned off during HALT2 or SLEEP mode, the one-frame period described above must elapse before the chip can be placed in standby mode.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 Split-Screen Display The LCD controller supports a split-screen function, allowing different images to be displayed on two vertically split screens on the LCD panel. To discriminate between these two screens, the upper half of the LCD panel is referred to as "screen 1" and the lower half is referred to as "screen 2".
VII LCD CONTROLLER BLOCK: LCD CONTROLLER The starting position of the view port is changed by modifying the screen 1 start address register described above. For example, when the start address is incremented by 16 bits, the pixel displayed at the 17th dot on line 1 moves to the beginning of the line, and the 16 leading pixels move off the screen. This is the basic operation for panning an image.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 Inverting and Blanking the Display The display can be blanked (the entire screen turned black) without rewriting the contents of the display memory. Setting DBLANK (D3)/LCDC mode register 1 (0x39FFE2) to "1" causes the FPDAT signal to go low, blanking the display. Setting it to "0" turns the display back on. Furthermore, the display can be inverted simply by manipulating bits.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER 4. Write a portrait-mode display image into memory, such as A → B ... C → D. 5. In the line byte-count register (0x39FFFC) for portrait-mode use, set the number of bytes equivalent to one virtual line of portrait display (256 pixels). For 8-bpp mode, with one pixel per byte, it is 256 bytes (0x100). Write 0x0 to the line byte-count register (0x39FFFC) for a one-byte line count. The value 0x0 is assumed to be 256 bytes per line.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 Alternate portrait mode Alternate portrait mode does not require extra display memory as in default portrait mode. To display the same horizontal 240-pixel image as in the above example, the display memory requires byte counts for only 240 pixels per line. Although alternate portrait mode provides higher display performance than default portrait mode, it requires a clock twice as fast at the same frame rate, resulting in larger current consumption.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER 7. If necessary, select the pixel clock frequency for use in portrait mode by using the PMODCLK[1:0] (D[1:0])/portrait mode register (0x39FFFB). Note that, in alternate portrait mode, the pixel clock frequency is halved compared to that in landscape mode, without specifically changing register settings. Therefore, the frame rate must be reviewed, including resetting of the non-display-period parameter.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 Power Save The LCD controller has two types of power-save modes. Use LPSAVE[1:0] (D[1:0])/LCDC mode register 2 (0x39FFE3) to set power-save modes. Table 2.17 Settings of Power-Save Modes LPSAVE1 LPSAVE0 0 0 1 1 0 1 0 1 Mode Power-save mode Reserved Doze mode Normal operation Power-save mode When the LCD controller enters this mode, all LCD signal output pins, including the LCDPWR pin, are dropped low, with the LCD panel placed in power-down mode.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER Controlling the GPIO Pins The pins described below can be used as general-purpose output (GPO) pins or general-purpose input/output (GPIO) pins, through panel selection or other settings. General-purpose output (GPO) pins The FPDAT[3:0] signal output pins can be used as general-purpose output GPO[6:3] pins when a 4-bit LCD panel (LDDW[1:0] (D[1:0])/0x39FFE1) = "00") is used. The GPO output control bits are listed in Table 2.19. Table 2.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 I/O Memory of LCD Controller Table 2.21 shows the control bits of the LCD controller. These registers are mapped into area 6 (0x39FFE0 to 0x39FFFD). Table 2.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER Register name Address Bit Vertical 039FFEA non-display (B) period register D7 D6 D5 D4 D3 D2 D1 D0 Name VNDPF – VNDP5 VNDP4 VNDP3 VNDP2 VNDP1 VNDP0 Function Setting Vertical non-display period status 1 VNDP 0 Display – reserved Non display period (lines) Vertical non-display period – Init. R/W Remarks 0 – 0 0 0 0 0 0 R – 0 when being read. R/W – 0 0 0 0 0 0 – 0 when being read.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 Register name Address Bit Name Screen 1 vertical size register 1 039FFF3 D7–2 – (B) D1 S1VSIZE9 D0 S1VSIZE8 FIFO control register 039FFF4 (B) D7 D6 D5 D4 D3 D2 D1 D0 Function Setting reserved Screen 1 vertical size (high-order 2 bits) – reserved FIFOEO3 FIFO empty offset FIFOEO2 FIFOEO1 FIFOEO0 LCLKSEL2 LCDC clock select LCLKSEL1 LCLKSEL0 – 0 0 – 0 when being read. R/W – Fix at 8 (0b1000) – 0 0 0 0 0 0 0 – 0 when being read.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER Register name Address Bit Name LCDC 039FFFD system control (B) register D7 D6 D5 D4 D3 D2 D1 D0 VRAMAR VRAMWT2 VRAMWT1 VRAMWT0 EDMAEN BREQEN LCDCST LCDCEC Function Setting VRAM area select 1 Area 8 VRAM wait control (number of wait cycles for SRAM) External DMA enable External bus-request enable A0/BSL select Big/little endian select 1 1 1 1 Init.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER BPP[1:0]: Bit-per-pixel select (D[7:6]) / LCDC mode register 1 (0x39FFE2) Selects display mode (bpp mode). The contents of selection, including that of LDCOLOR, are listed in Table 2.23. A-1 Table 2.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER LPWREN: Enable LCDPWR (D4) / LCDC mode register 2 (0x39FFE3) Enables LCDPWR output control by the LCD controller. Write "1": Enabled Write "0": Disabled Read: Valid When LPWREN is set to "1", the LCDPWR output is controlled by the LCD controller’s power-up/down sequence, allowing the power to the LCD panel to be turned ON or OFF using that signal. When LPWREN is set to "0", the LCDPWR pin is fixed low. At initial reset, LPWREN is set to "0" (disabled).
VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 VNDPF: Vertical non-display status (D7) / Vertical non-display period register (0x39FFEA) Indicates whether the LCD panel is in a vertical non-display period. Read "1": Vertical non-display period Read "0": Vertical display period Write: Invalid VNDPF is set to "1" during a vertical non-display period, and set to "0" during a vertical display period.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER LCLKSEL[2:0]: LCDC clock select (D[2:0]) / FIFO control register (0x39FFF4) Selects the operating clock for the LCD controller. The selected clock is used as the LCD controller’s pixel clock PCLK and display memory clock MCLK. The maximum clock frequency that can be supplied to the LCD controller is 25 MHz. Table 2.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 GPIO2D: GPIO2 data (D2) / GPIO status/control register (0x39FFF9) GPIO1D: GPIO1 data (D1) / GPIO status/control register (0x39FFF9) GPIO0D: GPIO0 data (D0) / GPIO status/control register (0x39FFF9) Input/output data for GPIO[2:0] pins.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER PMODSEL: Portrait mode select (D6) / Portrait mode register (0x39FFFB) Selects a type of portrait mode. Write "1": Alternate portrait mode Write "0": Default portrait mode Read: Valid Setting PMODSEL to "1" selects alternate portrait mode, and setting PMODSEL to "0" selects default portrait mode. When PMODEN (D7/0x39FFFB) is set to "1", data is displayed in the selected portrait mode. For details, refer to "Portrait Mode".
VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 EDMAEN: Enable external DMA (D3) / LCDC system control register (0x39FFFD) Enables/disables DMA requests from external devices while the LCD controller is in use. Write "1": Enabled Write "0": Disabled Read: Valid Setting EDMAEN to "1" enables DMA requests from other external devices even while the LCD controller is in use.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER Programming Notes (1) When the chip is set in HALT2 or SLEEP mode after the LCD controller is set in power-save mode, it is necessary to wait until all LCD signals are turned off by the controller’s power-down sequence (by default, a one-frame period). If the chip is placed in HALT2 or SLEEP mode while LCD signals are being output, the LCD panel may be damaged due to stoppage of the clock.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 Examples of LCD Controller Setting Program (Wait signal = ON) ;****************** ;C33L03 ASM ;****************** ;=================================== .org 0x0 .half 0x0008 .half 0x00c0 .org 0x0008 ;--------------------------;initial ;--------------------------xld.w %r1, 0x1fff ld.w %sp, %r1 ;stack poiter xld.w xld.w ld.b %r5, 0x48126 %r1, 0x0 [%r5], %r1 ;ROM access speed xld.w xld.w ld.
VII LCD CONTROLLER BLOCK: LCD CONTROLLER ld.b [%r1], %r2 xld.w xld.w ld.b %r1, 0x39ffea %r2, 0x01 [%r1], %r2 ; set Vertical Non-displayed Period xld.w xld.w ld.h %r1, 0x39ffec %r2, 0x0000 [%r1], %r2 ; set S1 start address aaaa xld.w xld.w ld.h %r1, 0x39ffee %r2, 0x0000 [%r1], %r2 ; set S2 start address 5555 xld.w xld.w ld.b %r1, 0x39fff1 %r2, 0x00 [%r1], %r2 ; set Memory address offset xld.w xld.w ld.h %r1, 0x39fff2 %r2, 0x0100 [%r1], %r2 ; set S1 Vertical size xld.w xld.w ld.
S1C33L03 FUNCTION PART Appendix I/O MAP
APPENDIX: I/O MAP A-1 Register name Address 8-bit timer 4/5 clock select register 0040140 (B) 8-bit timer 4/5 clock control register 0040145 (B) Bit Name D7–2 – D1 P8TPCK5 D0 P8TPCK4 D7 D6 D5 D4 D3 D2 D1 D0 P8TON5 P8TS52 P8TS51 P8TS50 P8TON4 P8TS42 P8TS41 P8TS40 Function reserved 8-bit timer 5 clock selection 8-bit timer 4 clock selection 8-bit timer 5 clock control 8-bit timer 5 clock division ratio selection 8-bit timer 4 clock control 8-bit timer 4 clock division ratio selection 8-bit ti
APPENDIX: I/O MAP Register name Address Bit Name Function 16-bit timer 3 clock control register 004014A D7–4 – (B) D3 P16TON3 D2 P16TS32 D1 P16TS31 D0 P16TS30 reserved 16-bit timer 3 clock control 16-bit timer 3 clock division ratio selection 16-bit timer 4 clock control register 004014B D7–4 – (B) D3 P16TON4 D2 P16TS42 D1 P16TS41 D0 P16TS40 reserved 16-bit timer 4 clock control 16-bit timer 4 clock division ratio selection 16-bit timer 5 clock control register 004014C D7–4 – (B) D3 P16TON5 D2 P
APPENDIX: I/O MAP A-1 Register name Address Bit Name 8-bit timer 2/3 clock control register D7 D6 D5 D4 P8TON3 P8TS32 P8TS31 P8TS30 004014E (B) D3 D2 D1 D0 P8TON2 P8TS22 P8TS21 P8TS20 A/D clock 004014F control register (B) D7–4 D3 D2 D1 D0 Clock timer Run/Stop register D7–2 – D1 TCRST D0 TCRUN 0040151 (B) Clock timer 0040152 interrupt (B) control register Clock timer 0040153 divider register (B) Clock timer second register 0040154 (B) – PSONAD PSAD2 PSAD1 PSAD0 Function 8-bit timer 3 cl
APPENDIX: I/O MAP Register name Address Bit Clock timer 0040155 minute register (B) D7–6 D5 D4 D3 D2 D1 D0 – TCHD5 TCHD4 TCHD3 TCHD2 TCHD1 TCHD0 reserved Clock timer minute counter data TCHD5 = MSB TCHD0 = LSB Clock timer hour register D7–5 D4 D3 D2 D1 D0 – TCDD4 TCDD3 TCDD2 TCDD1 TCDD0 Clock timer 0040157 day (low-order) (B) register D7 D6 D5 D4 D3 D2 D1 D0 Clock timer day (highorder) register 0040158 (B) Clock timer minute comparison register 0040159 (B) Clock timer hour comparison registe
APPENDIX: I/O MAP A-1 Register name Address Bit 8-bit timer 0 0040160 control register (B) D7–3 D2 D1 D0 Name Function – PTOUT0 PSET0 PTRUN0 reserved 8-bit timer 0 clock output control 8-bit timer 0 preset 8-bit timer 0 Run/Stop control Setting – 1 On 1 Preset 1 Run 0 Off 0 Invalid 0 Stop Init. R/W Remarks – 0 – 0 – 0 when being read. R/W W 0 when being read.
APPENDIX: I/O MAP Register name Address Bit Name Function 8-bit timer 3 004016C D7–3 – control register (B) D2 PTOUT3 D1 PSET3 D0 PTRUN3 reserved 8-bit timer 3 clock output control 8-bit timer 3 preset 8-bit timer 3 Run/Stop control 8-bit timer 3 reload data register 004016D (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD37 RLD36 RLD35 RLD34 RLD33 RLD32 RLD31 RLD30 8-bit timer 3 reload data RLD37 = MSB RLD30 = LSB 8-bit timer 3 counter data register 004016E (B) D7 D6 D5 D4 D3 D2 D1 D0 PTD37 PTD36 PTD35 PTD34
APPENDIX: I/O MAP A-1 Register name Address Bit Name Function Setting Init. R/W Remarks Watchdog 0040170 timer write(B) protect register D7 WRWD D6–0 – EWD write protection – 1 Write enabled 0 Write-protect – 0 – R/W – 0 when being read. Watchdog timer enable register D7–2 – D1 EWD D0 – – Watchdog timer enable – – 1 NMI enabled 0 NMI disabled – – 0 – – 0 when being read. R/W – 0 when being read.
APPENDIX: I/O MAP Register name Address Bit Name Power control register D7 D6 CLKDT1 CLKDT0 System clock division ratio selection D5 D4–3 D2 D1 D0 PSCON – CLKCHG SOSC3 SOSC1 Prescaler On/Off control reserved 1 OSC3 CPU operating clock switch High-speed (OSC3) oscillation On/Off 1 On Low-speed (OSC1) oscillation On/Off 1 On 0040180 (B) Function Setting CLKDT[1:0] 1 1 1 0 0 1 0 0 1 On R/W 1 0 1 1 1 R/W – Writing 1 not allowed. R/W R/W R/W – 0 0 – R/W – 0 1 0 0 – 0 when being read.
APPENDIX: I/O MAP A-1 Register name Address Bit Name Function Serial I/F Ch.0 transmit data register 00401E0 (B) D7 D6 D5 D4 D3 D2 D1 D0 TXD07 TXD06 TXD05 TXD04 TXD03 TXD02 TXD01 TXD00 Serial I/F Ch.0 transmit data TXD07(06) = MSB TXD00 = LSB 0x0 to 0xFF(0x7F) X X X X X X X X Serial I/F Ch.0 receive data register 00401E1 (B) D7 D6 D5 D4 D3 D2 D1 D0 RXD07 RXD06 RXD05 RXD04 RXD03 RXD02 RXD01 RXD00 Serial I/F Ch.
APPENDIX: I/O MAP Register name Address Bit Serial I/F Ch.1 transmit data register 00401E5 (B) D7 D6 D5 D4 D3 D2 D1 D0 TXD17 TXD16 TXD15 TXD14 TXD13 TXD12 TXD11 TXD10 Name Serial I/F Ch.1 transmit data TXD17(16) = MSB TXD10 = LSB Function 0x0 to 0xFF(0x7F) X X X X X X X X Serial I/F Ch.1 receive data register 00401E6 (B) D7 D6 D5 D4 D3 D2 D1 D0 RXD17 RXD16 RXD15 RXD14 RXD13 RXD12 RXD11 RXD10 Serial I/F Ch.
APPENDIX: I/O MAP A-1 Register name Address Bit Name Function Serial I/F Ch.2 00401F3 control register (B) D7 D6 D5 D4 D3 D2 D1 D0 TXEN2 RXEN2 EPR2 PMD2 STPB2 SSCK2 SMD21 SMD20 Ch.2 transmit enable Ch.2 receive enable Ch.2 parity enable Ch.2 parity mode selection Ch.2 stop bit selection Ch.2 input clock selection Ch.2 transfer mode selection – DIVMD2 IRTL2 IRRL2 IRMD21 IRMD20 reserved Ch.2 async. clock division ratio Ch.2 IrDA I/F output logic inversion Ch.2 IrDA I/F input logic inversion Ch.
APPENDIX: I/O MAP Register name Address Bit A/D conversion 0040240 result (low(B) order) register D7 D6 D5 D4 D3 D2 D1 D0 Name ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 Function 0 0 0 0 0 0 0 0 R – 0x0 to 0x3FF (high-order 2 bits) – 0 0 – R – – 0 0 0 D7–2 – D1 ADD9 D0 ADD8 – A/D converted data (high-order 2 bits) ADD9 = MSB A/D trigger register D7–6 D5 D4 D3 – MS TS1 TS0 – A/D conversion mode selection A/D conversion trigger selection D2 D1 D0 CH2 CH1 CH0 A/D conversion channel status
APPENDIX: I/O MAP A-1 Register name Address Bit Port input 0/1 0040260 interrupt (B) priority register D7 D6 D5 D4 D3 D2 D1 D0 – PP1L2 PP1L1 PP1L0 – PP0L2 PP0L1 PP0L0 reserved Port input 1 interrupt level – 0 to 7 reserved Port input 0 interrupt level – 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 – PP3L2 PP3L1 PP3L0 – PP2L2 PP2L1 PP2L0 reserved Port input 3 interrupt level – 0 to 7 reserved Port input 2 interrupt level – 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 – PK1L2 PK1L1 PK1L0 – PK0L2 PK0L1 PK0L0 reserved Ke
APPENDIX: I/O MAP Register name Address Bit 8-bit timer, 0040269 serial I/F Ch.0 (B) interrupt priority register D7 D6 D5 D4 D3 D2 D1 D0 – PSIO02 PSIO01 PSIO00 – P8TM2 P8TM1 P8TM0 reserved Serial interface Ch.0 interrupt level – 0 to 7 reserved 8-bit timer 0–3 interrupt level – 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 – PAD2 PAD1 PAD0 – PSIO12 PSIO11 PSIO10 reserved A/D converter interrupt level – 0 to 7 reserved Serial interface Ch.
APPENDIX: I/O MAP A-1 Register name Address Bit Name Function Key input, 0040270 port input 0–3 (B) interrupt enable register D7–6 D5 D4 D3 D2 D1 D0 – EK1 EK0 EP3 EP2 EP1 EP0 reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 DMA interrupt 0040271 enable register (B) D7–5 D4 D3 D2 D1 D0 – EIDMA EHDM3 EHDM2 EHDM1 EHDM0 reserved IDMA High-speed DMA Ch.3 High-speed DMA Ch.2 High-speed DMA Ch.1 High-speed DMA Ch.
APPENDIX: I/O MAP Register name Address Bit Key input, 0040280 port input 0–3 (B) interrupt factor flag register D7–6 D5 D4 D3 D2 D1 D0 – FK1 FK0 FP3 FP2 FP1 FP0 Name reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 Function DMA interrupt factor flag register 0040281 (B) D7–5 D4 D3 D2 D1 D0 – FIDMA FHDM3 FHDM2 FHDM1 FHDM0 reserved IDMA High-speed DMA Ch.3 High-speed DMA Ch.2 High-speed DMA Ch.1 High-speed DMA Ch.
APPENDIX: I/O MAP A-1 Register name Address Bit Name Port input 0–3, high-speed DMA Ch. 0/1, 16-bit timer 0 IDMA request register 0040290 (B) D7 D6 D5 D4 D3 D2 D1 D0 R16TC0 R16TU0 RHDM1 RHDM0 RP3 RP2 RP1 RP0 16-bit timer 0 comparison A 16-bit timer 0 comparison B High-speed DMA Ch.1 High-speed DMA Ch.
APPENDIX: I/O MAP Register name Address Bit Name High-speed DMA Ch.0/1 trigger set-up register D7 D6 D5 D4 HSD1S3 HSD1S2 HSD1S1 HSD1S0 High-speed DMA Ch.1 trigger set-up D3 D2 D1 D0 HSD0S3 HSD0S2 HSD0S1 HSD0S0 High-speed DMA Ch.0 trigger set-up D7 D6 D5 D4 HSD3S3 HSD3S2 HSD3S1 HSD3S0 High-speed DMA Ch.3 trigger set-up D3 D2 D1 D0 HSD2S3 HSD2S2 HSD2S1 HSD2S0 High-speed DMA Ch.2 trigger set-up High-speed DMA Ch.
APPENDIX: I/O MAP A-1 Register name Address Bit Name Function K5 function select register 00402C0 D7–5 – (B) D4 CFK54 D3 CFK53 D2 CFK52 D1 CFK51 D0 CFK50 reserved K54 function selection K53 function selection K52 function selection K51 function selection K50 function selection K5 input port data register 00402C1 D7–5 – (B) D4 K54D D3 K53D D2 K52D D1 K51D D0 K50D reserved K54 input port data K53 input port data K52 input port data K51 input port data K50 input port data K6 function select register
APPENDIX: I/O MAP Register name Address Bit Interrupt factor 00402C5 FP function switching register D7 D6 T8CH5S0 SIO3TS0 8-bit timer 5 underflow SIO Ch.3 transmit buffer empty D5 D4 T8CH4S0 SIO3RS0 8-bit timer 4 underflow SIO Ch.3 receive buffer full D3 SIO2TS0 SIO Ch.2 transmit buffer empty D2 SIO3ES0 SIO Ch.3 receive error D1 SIO2RS0 SIO Ch.2 receive buffer full D0 SIO2ES0 SIO Ch.
APPENDIX: I/O MAP A-1 Register name Address Bit Name Function Key input interrupt (FPK0) input comparison register 00402CC D7–5 – (B) D4 SCPK04 D3 SCPK03 D2 SCPK02 D1 SCPK01 D0 SCPK00 reserved FPK04 input comparison FPK03 input comparison FPK02 input comparison FPK01 input comparison FPK00 input comparison Key input interrupt (FPK1) input comparison register 00402CD D7–4 – (B) D3 SCPK13 D2 SCPK12 D1 SCPK11 D0 SCPK10 reserved FPK13 input comparison FPK12 input comparison FPK11 input comparison FPK1
APPENDIX: I/O MAP Register name Address Bit P1 I/O control register 00402D6 (B) D7 D6 D5 D4 D3 D2 D1 D0 Port SIO function extension register 00402D7 D7–4 – D3 SSRDY3 reserved Serial I/F Ch.3 SRDY selection 1 #SRDY3 D2 SSCLK3 Serial I/F Ch.3 SCLK selection 1 #SCLK3 D1 SSOUT3 Serial I/F Ch.3 SOUT selection 1 SOUT3 D0 SSIN3 Serial I/F Ch.
APPENDIX: I/O MAP A-1 Register name Address Bit Port function extension register D7 D6 D5 D4 D3 D2 D1 CFEX7 CFEX6 CFEX5 CFEX4 CFEX3 CFEX2 CFEX1 P07 port extended function P06 port extended function P05 port extended function P04 port extended function P31 port extended function P21 port extended function P10, P11, P13 port extended function D0 CFEX0 P12, P14 port extended function DF DE DD DC – A18SZ A18DF1 A18DF0 DB DA D9 D8 – A18WT2 A18WT1 A18WT0 D7 D6 D5 D4 – A16SZ A16DF1 A16DF0 D3 D2 D1
APPENDIX: I/O MAP Register name Address Bit Areas 12–11 0048124 set-up register (HW) DF–7 D6 D5 D4 – A12SZ A12DF1 A12DF0 D3 D2 D1 D0 – A12WT2 A12WT1 A12WT0 DF DE DD DC Areas 10–9 0048126 set-up register (HW) Areas 8–7 0048128 set-up register (HW) B-APPENDIX-24 Name Function Setting Init. R/W Remarks reserved – Areas 12–11 device size selection 1 8 bits 0 16 bits Areas 12–11 A18DF[1:0] Number of cycles 1 1 3.5 output disable delay time 1 0 2.5 0 1 1.5 0 0 0.
APPENDIX: I/O MAP A-1 Register name Address Bit Name Areas 6–4 004812A DF–E – set-up register (HW) DD A6DF1 DC A6DF0 Function reserved Area 6 output disable delay time Setting – Number of cycles 3.5 2.5 1.5 0.5 – A6WT[2:0] Wait cycles 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 – 1 8 bits 0 16 bits A5DF[1:0] Number of cycles 1 1 3.5 1 0 2.5 0 1 1.5 0 0 0.5 A6DF[1:0] 1 1 1 0 0 1 0 0 Init. R/W Remarks – 1 1 – 0 when being read. R/W – 1 1 1 – 0 when being read.
APPENDIX: I/O MAP Register name Address Bit Name Function DRAM timing 0048130 DF–C – reserved set-up register (HW) DB A3EEN Area 3 emulation DA CEFUNC1 #CE pin function selection D9 CEFUNC0 Setting Init. R/W Remarks – 1 Internal ROM 0 Emulation CEFUNC[1:0] #CE output 1 x #CE7/8..#CE17/18 #CE6..#CE17 0 1 #CE4..
APPENDIX: I/O MAP A-1 Register name Address Bit G/A read signal 0048138 control register (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BCLK select register Name A18AS A16AS A14AS A12AS – A8AS A6AS A5AS A18RD A16RD A14RD A12RD – A8RD A6RD A5RD 004813A D7–4 – (B) D3 A1X1MD D2 – D1 BCLKSEL1 D0 BCLKSEL0 Function Area 18, 17 address strobe signal Area 16, 15 address strobe signal Area 14, 13 address strobe signal Area 12, 11 address strobe signal reserved Area 8, 7 address strobe signal Area 6 add
APPENDIX: I/O MAP Register name Address Bit Name Function Setting 16-bit timer 0 comparison register A 0048180 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR0A15 CR0A14 CR0A13 CR0A12 CR0A11 CR0A10 CR0A9 CR0A8 CR0A7 CR0A6 CR0A5 CR0A4 CR0A3 CR0A2 CR0A1 CR0A0 16-bit timer 0 comparison data A CR0A15 = MSB CR0A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 0 comparison register B 0048182 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR0B15 CR0B14 CR0B13 CR0B1
APPENDIX: I/O MAP A-1 Register name Address Bit Name Function Setting 16-bit timer 1 comparison register A 0048188 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 1 comparison register B 004818A (HW) 16-bit timer 1 counter data register CR1A15 CR1A14 CR1A13 CR1A12 CR1A11 CR1A10 CR1A9 CR1A8 CR1A7 CR1A6 CR1A5 CR1A4 CR1A3 CR1A2 CR1A1 CR1A0 16-bit timer 1 comparison data A CR1A15 = MSB CR1A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W DF DE DD DC DB DA D9 D8 D7 D6 D5
APPENDIX: I/O MAP Register name Address Bit Name Function Setting 16-bit timer 2 comparison register A 0048190 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR2A15 CR2A14 CR2A13 CR2A12 CR2A11 CR2A10 CR2A9 CR2A8 CR2A7 CR2A6 CR2A5 CR2A4 CR2A3 CR2A2 CR2A1 CR2A0 16-bit timer 2 comparison data A CR2A15 = MSB CR2A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 2 comparison register B 0048192 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR2B15 CR2B14 CR2B13 CR2B1
APPENDIX: I/O MAP A-1 Register name Address Bit Name Function Setting 16-bit timer 3 comparison register A 0048198 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 3 comparison register B 004819A (HW) 16-bit timer 3 counter data register CR3A15 CR3A14 CR3A13 CR3A12 CR3A11 CR3A10 CR3A9 CR3A8 CR3A7 CR3A6 CR3A5 CR3A4 CR3A3 CR3A2 CR3A1 CR3A0 16-bit timer 3 comparison data A CR3A15 = MSB CR3A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W DF DE DD DC DB DA D9 D8 D7 D6 D5
APPENDIX: I/O MAP Register name Address Bit Name Function Setting 16-bit timer 4 comparison register A 00481A0 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR4A15 CR4A14 CR4A13 CR4A12 CR4A11 CR4A10 CR4A9 CR4A8 CR4A7 CR4A6 CR4A5 CR4A4 CR4A3 CR4A2 CR4A1 CR4A0 16-bit timer 4 comparison data A CR4A15 = MSB CR4A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 4 comparison register B 00481A2 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR4B15 CR4B14 CR4B13 CR4B1
APPENDIX: I/O MAP A-1 Register name Address Bit Name Function Setting 16-bit timer 5 comparison register A 00481A8 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 5 comparison register B 00481AA (HW) 16-bit timer 5 counter data register CR5A15 CR5A14 CR5A13 CR5A12 CR5A11 CR5A10 CR5A9 CR5A8 CR5A7 CR5A6 CR5A5 CR5A4 CR5A3 CR5A2 CR5A1 CR5A0 16-bit timer 5 comparison data A CR5A15 = MSB CR5A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W DF DE DD DC DB DA D9 D8 D7 D6 D5
APPENDIX: I/O MAP Register name Address Bit IDMA base address loworder register 0048200 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IDMA base address high-order register 0048202 DF–C – (HW) DB DBASEH11 DA DBASEH10 D9 DBASEH9 D8 DBASEH8 D7 DBASEH7 D6 DBASEH6 D5 DBASEH5 D4 DBASEH4 D3 DBASEH3 D2 DBASEH2 D1 DBASEH1 D0 DBASEH0 reserved IDMA base address high-order 12 bits (Initial value: 0x0C003A0) IDMA start register 0048204 (B) D7 DSTART D6–0 DCHN IDMA start IDMA channel number 1 IDMA sta
APPENDIX: I/O MAP A-1 Register name Address Bit Name High-speed DMA Ch.0 transfer counter register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC0_L7 TC0_L6 TC0_L5 TC0_L4 TC0_L3 TC0_L2 TC0_L1 TC0_L0 BLKLEN07 BLKLEN06 BLKLEN05 BLKLEN04 BLKLEN03 BLKLEN02 BLKLEN01 BLKLEN00 Ch.0 transfer counter[7:0] (block transfer mode) DF DE DUALM0 D0DIR DD–8 D7 D6 D5 D4 D3 D2 D1 D0 – TC0_H7 TC0_H6 TC0_H5 TC0_H4 TC0_H3 TC0_H2 TC0_H1 TC0_H0 Ch.0 address mode selection D) Invalid S) Ch.
APPENDIX: I/O MAP Register name Address Bit High-speed 0048228 DMA Ch.0 (HW) low-order destination address set-up register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D0ADRL15 D) Ch.0 destination address[15:0] D0ADRL14 S) Invalid D0ADRL13 D0ADRL12 D0ADRL11 D0ADRL10 D0ADRL9 D0ADRL8 D0ADRL7 D0ADRL6 D0ADRL5 D0ADRL4 D0ADRL3 D0ADRL2 D0ADRL1 D0ADRL0 DF DE D0MOD1 D0MOD0 Ch.0 transfer mode DD DC D0IN1 D0IN0 D) Ch.
APPENDIX: I/O MAP A-1 Register name Address Bit Name High-speed DMA Ch.1 transfer counter register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC1_L7 TC1_L6 TC1_L5 TC1_L4 TC1_L3 TC1_L2 TC1_L1 TC1_L0 BLKLEN17 BLKLEN16 BLKLEN15 BLKLEN14 BLKLEN13 BLKLEN12 BLKLEN11 BLKLEN10 Ch.1 transfer counter[7:0] (block transfer mode) DF DE DUALM1 D1DIR DD–8 D7 D6 D5 D4 D3 D2 D1 D0 – TC1_H7 TC1_H6 TC1_H5 TC1_H4 TC1_H3 TC1_H2 TC1_H1 TC1_H0 Ch.1 address mode selection D) Invalid S) Ch.
APPENDIX: I/O MAP Register name Address Bit High-speed 0048238 DMA Ch.1 (HW) low-order destination address set-up register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D1ADRL15 D) Ch.1 destination address[15:0] D1ADRL14 S) Invalid D1ADRL13 D1ADRL12 D1ADRL11 D1ADRL10 D1ADRL9 D1ADRL8 D1ADRL7 D1ADRL6 D1ADRL5 D1ADRL4 D1ADRL3 D1ADRL2 D1ADRL1 D1ADRL0 DF DE D1MOD1 D1MOD0 Ch.1 transfer mode DD DC D1IN1 D1IN0 D) Ch.
APPENDIX: I/O MAP A-1 Register name Address Bit Name High-speed DMA Ch.2 transfer counter register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC2_L7 TC2_L6 TC2_L5 TC2_L4 TC2_L3 TC2_L2 TC2_L1 TC2_L0 BLKLEN27 BLKLEN26 BLKLEN25 BLKLEN24 BLKLEN23 BLKLEN22 BLKLEN21 BLKLEN20 Ch.2 transfer counter[7:0] (block transfer mode) DF DE DUALM2 D2DIR DD–8 D7 D6 D5 D4 D3 D2 D1 D0 – TC2_H7 TC2_H6 TC2_H5 TC2_H4 TC2_H3 TC2_H2 TC2_H1 TC2_H0 Ch.2 address mode selection D) Invalid S) Ch.
APPENDIX: I/O MAP Register name Address Bit High-speed 0048248 DMA Ch.2 (HW) low-order destination address set-up register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D2ADRL15 D) Ch.2 destination address[15:0] D2ADRL14 S) Invalid D2ADRL13 D2ADRL12 D2ADRL11 D2ADRL10 D2ADRL9 D2ADRL8 D2ADRL7 D2ADRL6 D2ADRL5 D2ADRL4 D2ADRL3 D2ADRL2 D2ADRL1 D2ADRL0 DF DE D2MOD1 D2MOD0 Ch.2 transfer mode DD DC D2IN1 D2IN0 D) Ch.
APPENDIX: I/O MAP A-1 Register name Address Bit Name High-speed DMA Ch.3 transfer counter register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC3_L7 TC3_L6 TC3_L5 TC3_L4 TC3_L3 TC3_L2 TC3_L1 TC3_L0 BLKLEN37 BLKLEN36 BLKLEN35 BLKLEN34 BLKLEN33 BLKLEN32 BLKLEN31 BLKLEN30 Ch.3 transfer counter[7:0] (block transfer mode) DF DE DUALM3 D3DIR DD–8 D7 D6 D5 D4 D3 D2 D1 D0 – TC3_H7 TC3_H6 TC3_H5 TC3_H4 TC3_H3 TC3_H2 TC3_H1 TC3_H0 Ch.3 address mode selection D) Invalid S) Ch.
APPENDIX: I/O MAP Register name Address Bit High-speed 0048258 DMA Ch.3 (HW) low-order destination address set-up register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D3ADRL15 D) Ch.3 destination address[15:0] D3ADRL14 S) Invalid D3ADRL13 D3ADRL12 D3ADRL11 D3ADRL10 D3ADRL9 D3ADRL8 D3ADRL7 D3ADRL6 D3ADRL5 D3ADRL4 D3ADRL3 D3ADRL2 D3ADRL1 D3ADRL0 DF DE D3MOD1 D3MOD0 Ch.3 transfer mode DD DC D3IN1 D3IN0 D) Ch.
APPENDIX: I/O MAP A-1 Register name Address SDRAM area configuration register 039FFC0 (B) SDRAM 039FFC1 control register (B) Bit Name SDRAR0 SDRAR1 – SDRPC0 SDRPC1 – Area 7/13 configuration Area 8/14 configuration reserved #CE7/13 pin configuration #CE8/14 pin configuration reserved 1 SDRAM 1 SDRAM D7 D6 D5 D4 SDRENA SDRINI SDRSRF SDRIS Enable SDRAM signals Start SDRAM power up Enable SDRAM self-refresh Initial command sequence 1 1 1 1 039FFC2 D7 – (B) D6–5 SDRCA1 SDRCA0 D4 – D3–2 SDRRA1 SDRR
APPENDIX: I/O MAP Register name Address SDRAM timing set-up register 2 Bit Name Function 039FFC5 D7–6 SDRTRCD1 SDRAM tRCD spec (B) SDRTRCD0 0 0 0 R/W R/W – – – 0 to 4096 – 1 1 1 1 1 1 1 1 1 1 1 1 – 0 when being read. R/W – 2 to 15 – 1 1 1 1 – 0 when being read. R/W This register must not be set less than "0x02". reserved – 1 8 bits 0 16 bits SDRAM data path bit width SDRAM bank interleaved access 1 Interleaved 0 One bank – reserved – 0 0 – – 0 when being read. R/W R/W – 0 when being read.
APPENDIX: I/O MAP A-1 Register name Address Bit Name Revision code register D7 D6 D5 D4 D3 D2 D1 D0 PCODE5 PCODE4 PCODE3 PCODE2 PCODE1 PCODE0 RCODE1 RCODE0 LCDC mode register 0 LCDC mode register 1 039FFE0 (B) Revision code 039FFE2 (B) BPP1 BPP0 Bit-per-pixel select (Display mode) – DBLANK FRMRPT – INVDISP reserved Blank display Frame repeat for EL panel reserved Invert display 039FFE3 D7–6 – (B) D5 LCDCEN D4 LPWREN D3–2 – D1 LPSAVE1 D0 LPSAVE0 Init.
APPENDIX: I/O MAP Register name Address Bit Vertical 039FFEA non-display (B) period register D7 D6 D5 D4 D3 D2 D1 D0 Name VNDPF – VNDP5 VNDP4 VNDP3 VNDP2 VNDP1 VNDP0 Function Setting Vertical non-display period status 1 VNDP 0 Display – reserved Non display period (lines) Vertical non-display period – Init. R/W Remarks 0 – 0 0 0 0 0 0 R – 0 when being read. R/W – 0 0 0 0 0 0 – 0 when being read.
APPENDIX: I/O MAP A-1 Register name Address Bit Name Screen 1 vertical size register 1 039FFF3 D7–2 – (B) D1 S1VSIZE9 D0 S1VSIZE8 FIFO control register 039FFF4 (B) D7 D6 D5 D4 D3 D2 D1 D0 Function Setting reserved Screen 1 vertical size (high-order 2 bits) – reserved FIFOEO3 FIFO empty offset FIFOEO2 FIFOEO1 FIFOEO0 LCLKSEL2 LCDC clock select LCLKSEL1 LCLKSEL0 – 0 0 – 0 when being read. R/W – Fix at 8 (0b1000) – 0 0 0 0 0 0 0 – 0 when being read. R/W – 0 0 0 0 – 0 when being read.
APPENDIX: I/O MAP Register name Address Bit Name LCDC 039FFFD system control (B) register D7 D6 D5 D4 D3 D2 D1 D0 VRAMAR VRAMWT2 VRAMWT1 VRAMWT0 EDMAEN BREQEN LCDCST LCDCEC B-APPENDIX-48 Function Setting VRAM area select 1 Area 8 VRAM wait control (number of wait cycles for SRAM) External DMA enable External bus-request enable A0/BSL select Big/little endian select EPSON 1 1 1 1 Init.
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S1C33L03 Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epsondevice.
